MICROPROCESSOR AND ITS APPLICATIONS (EC-501) - Unit 5 Short Notes

UNIT 5: MICROPROCESSOR AND ITS APPLICATIONS

I. 8086/88 MICROPROCESSOR FUNDAMENTALS

Architecture & Organization

• Bus Interface Unit (BIU): Handles all bus operations (address generation, instruction fetch, read/write). Contains Instruction Queue (6 bytes).

• Execution Unit (EU): Executes instructions. Contains ALU, registers, control circuitry. Requests bus cycles from BIU.

• Register Organization:

  | Register Type | Registers | Primary Function | | :--- | :--- | :--- | | General Purpose | AX, BX, CX, DX | 16-bit; can be used as 8-bit (AH/AL, etc.). AX for I/O, BX for addressing, CX for count/rep, DX for port address/MUL. | | Segment | CS, DS, SS, ES | Hold 16-bit segment selectors. Physical address = Segment × 16 + Offset. | | Pointer/Index | SP, BP, SI, DI | SP for stack, BP for base, SI/DI for string/memory. | | Flag | FLAGS (16-bit) | Status & control flags (CF, PF, AF, ZF, SF, TF, IF, DF, OF). |

• Memory Organization:

  • Segmentation: 1MB memory (00000H–FFFFFH) divided into 16 segments of 64KB each.

  • Physical Address Calculation: PA = (Segment Register × 10H) + Offset.

  • Even/Odd Bank Organization: Memory organized as two 8-bit banks. Even addresses (A0=0) use lower bank; Odd addresses (A0=1) use upper bank. BHE# (Bus High Enable) signal controls upper bank.

• Minimum vs. Maximum Mode:

  • Minimum Mode (MN/MX# = 1): 8086 generates all control signals (RD#, WR#, M/IO#, ALE, DEN, DT/R). Used in single-processor systems.

  • Maximum Mode (MN/MX# = 0): Control signals generated by external bus controller (8288). Supports multiprocessor systems. Status signals S0#–S2# indicate cycle type.

Timing Diagrams

• Memory Read Cycle (Minimum Mode):

  1. T1: Address (A19–S6, A15–A0) placed on bus. ALE goes HIGH to latch address. M/IO# HIGH (memory). Status codes S2#S1#S0# = 001 (interrupt acknowledge) or others.

  2. T2: Addresses floated. RD# goes LOW. Data bus driven by memory.

  3. T3: Data valid on bus. DEN goes LOW to enable transceivers. DT/R HIGH (read).

  4. T4: RD# goes HIGH. Data may be held. DEN goes HIGH.

  [!TIP] Common Pitfall: Forgetting that BHE# is also part of the address in T1 for word access on odd boundary.

• Timing for Instructions (LXI H, MVI A): Shows number of machine cycles (M1 for opcode fetch, M2/M3 for memory read/write) and states (T1–T4/T5).

Instruction Set & Addressing Modes

• Classification:

  • Data Transfer: MOV, PUSH, POP, XCHG, IN, OUT, LEA, LDS, LES.

  • Arithmetic: ADD, ADC, SUB, SBB, INC, DEC, MUL, IMUL, DIV, IDIV, AAA, DAA.

  • Logical: AND, OR, XOR, TEST, NOT, SHL/SAL, SHR, SAR, ROL, ROR, RCL, RCR.

  • Branch: JMP, CALL, RET, Jcc (JE, JNE, JL, etc.).

  • Loop: LOOP, LOOPE/LOOPNE.

  • String: MOVS, CMPS, SCAS, LODS, STOS (with REP prefix).

  • Flag: STC, CLC, STD, CLD, STI, CLI, SAHF, LAHF, PUSHF, POPF.

• Addressing Modes (with examples):

  | Mode | Syntax | Offset Calculation | Example | | :--- | :--- | :--- | :--- | | Immediate | MOV AX, 1234H | Operand in instruction | ADD BX, 5000H | | Register | MOV AX, BX | Operand in register | INC CX | | Direct | MOV AX, [5000H] | 16-bit displacement | ADD [3000H], BL | | Register Indirect | MOV AX, [BX] | Offset from BX, SI, DI, BP | ADD [SI], CL | | Indexed | MOV AX, [SI+10H] | SI/DI + 8/16-bit disp | MOV AL, [DI-5] | | Based | MOV AX, [BP+10H] | BX/BP + 8/16-bit disp | ADD [BP+4], AH | | Based-Indexed | MOV AX, [BX+SI] | BX/BP + SI/DI | MOV [BX+DI], CL | | Based-Indexed+Disp | MOV AX, [BX+SI+10H] | BX/BP + SI/DI + disp | ADD [BP+DI+2], AL | | Relative Based-Indexed| JMP [BX+SI+10H] | For branch only | JMP [BX+DI-5] |

  Effective Address (Offset): 16-bit computed offset within a segment.

• Key Instruction Explanations:

  • CMP: CMP dest, src → dest - src; sets flags (SF, ZF, CF, OF, PF, AF) but doesn't store result.

  • PUSHF: Push FLAGS register onto stack (SP ← SP–2, [SS:SP] ← FLAGS).

  • SAR (Shift Arithmetic Right): Preserves sign bit (MSB). SAR CX, 1 → CX = CX/2 (signed).

  • RCL (Rotate Through Carry Left): RCL dest, count. MSB → CF, CF → LSB, all bits rotate left through carry.

Assembly Language Programming

• Program Structure: ASSUME CS:CODE, DS:DATA → DATA SEGMENT → ... → DATA ENDS → CODE SEGMENT → START: MOV AX, DATA → MOV DS, AX → ... → MOV AH, 4CH → INT 21H → CODE ENDS → END START.

• Directives: ORG (origin), END (program end), ASSUME (segment register association).

• Data Copy/Transfer: MOV (register/memory), PUSH/POP (stack), XCHG (exchange), IN/OUT (I/O), LEA (load effective address), LDS/LES (load DS/ES and a register).

• Example: Find Largest in Array (N=10):

  
  MOV SI, OFFSET ARRAY  ; SI points to array
  
  MOV CL, 10            ; Counter
  
  MOV AL, [SI]          ; Assume first element is max
  
  DEC CL
  
  BACK: INC SI
  
        CMP AL, [SI]
  
        JAE SKIP         ; Jump if AL >= [SI]
  
        MOV AL, [SI]     ; New max found
  
  SKIP: LOOP BACK
  
  MOV MAX, AL
  
  

• String Operations: MOVSB (move byte from [SI] to [DI]), CMPSB (compare), SCASB (scan), REP/REPE/REPNE prefixes for repetition based on CX.

II. MEMORY AND I/O INTERFACING

Memory Interfacing Concepts

• Address Decoding:

  • Absolute Decoding: All address lines used to select a chip. Unique address for each chip. No address overlap.

  • Partial Decoding: Only higher-order address lines used. Multiple addresses map to same chip (aliasing). Simpler hardware but wastes address space.

• Memory Map Design: Select appropriate chips (RAM/ROM) and assign address ranges based on system memory map (e.g., 00000H–7FFFFH for RAM, F8000H–FFFFFH for ROM).

• Interfacing Example (32KB RAM + 2x4KB EPROM):

  • RAM: 32KB = 2 × 16KB chips. Use A15 to select between two 16KB chips. Chip select logic: CS1 = A15', CS2 = A15.

  • EPROMs: 4KB each → 13 address lines (A0–A12). A13, A14 select between two EPROMs and RAM. Example: EPROM1 (00000H–00FFFH), EPROM2 (01000H–01FFFH), RAM (02000H–0FFFFH).

I/O Interfacing Concepts

• I/O-Mapped I/O (Port-Mapped):

  • Separate control signal M/IO# (LOW for I/O).

  • Uses IN/OUT instructions.

  • Full 16-bit address space available for I/O (64K ports).

  • No memory bus contention.

• Memory-Mapped I/O:

  • No M/IO# distinction. I/O ports treated as memory locations.

  • Uses any memory-access instruction (MOV, ADD, etc.).

  • Reduces available memory address space.

  • Simpler control logic.

III. PROGRAMMABLE PERIPHERAL INTERFACE (8255)

Block Diagram & Pin Diagram

• Data Bus Buffer: 8-bit bidirectional, connects to system data bus.

• Read/Write Control Logic: Manages chip select (CS#), read (RD#), write (WR#) and generates control signals for ports.

• Group A & Group B Control: Each group has control register (Port A + PC_upper, Port B + PC_lower).

• Ports A, B, C: 8-bit ports. Port C can be split into two 4-bit parts.

Operating Modes

• Mode 0 (Basic I/O): Simple input/output. No handshaking. Ports A, B, C (as two 4-bit ports) can be input/output.

• Mode 1 (Strobed I/O): Handshaking signals (STB, IBF, OBF, ACK, INTR). Only Ports A & B. PC pins assigned handshake functions.

  • Input Mode: STB (Strobe) loads data, IBF (Input Buffer Full) signals full, INTR (interrupt request) on rising edge of STB if enabled.

  • Output Mode: CPU writes data, OBF (Output Buffer Full) signals data ready, peripheral sends ACK to clear OBF, INTR on falling edge of ACK if enabled.

• Mode 2 (Bidirectional Bus): Only for Port A. Uses PC_upper (PC4–PC7) for handshaking (INTR, IBF, OBF, ACK, STB). Allows data flow in both directions.

• Bit Set/Reset (BSR) Mode: Individual bit control of Port C. Control word format: D7=0, D6-D3=000, D2-D0=bit select. D1=1 (set), D1=0 (reset). Used for generating square wave on a single pin.

Control Word Format

• Mode Set Format (D7=1):

  
  D7 D6 D5 | D4 D3 | D2 D1 D0
  
  ---------------------------
  
  1  | Mode A | Mode B | Port C Upper | Port B | Port A
  
  (1=Mode1, 0=Mode0)   (1=Input, 0=Output)
  
  

• BSR Format (D7=0): 0 0 0 D2 D1 D0 (bit select), D (set/reset bit).

Interfacing with 8086

• Connect D0–D7 to data bus. Use A0 to select between Port A/B (even) and Port C/Control (odd).

• I/O Address Assignment: Example: Port A=00H, Port B=02H, Port C=04H, Control=06H.

• 8086 to 8255 (Low Byte): OUT 06H, AL (write control), IN AL, 00H (read Port A).

Applications

• Keyboard/display interfacing (matrix).

• Generating control signals (BSR mode).

• Interfacing switches/LEDs.

IV. PROGRAMMABLE INTERRUPT CONTROLLER (8259A)

Block Diagram & Functional Blocks

• Interrupt Request Register (IRR): Holds pending interrupt requests (IR0–IR7).

• In-Service Register (ISR): Holds interrupts being serviced.

• Priority Resolver: Determines highest priority pending interrupt (IR0 highest, IR7 lowest in fixed nested mode).

• Interrupt Mask Register (IMR): Masks interrupts (1=masked).

• Control Logic: Generates INT output to CPU, handles INTA cycles.

• Data Bus Buffer: For read/write of registers.

• Read/Write Logic: Decodes CS#, RD#, WR#, A0.

Modes of Operation

• Fully Nested Mode: Default. IR0 highest priority. Lower priority interrupts can be nested if not masked.

• Automatic Rotation: After servicing an interrupt, its priority becomes lowest. Ensures fairness.

• Specific Rotation: Software sets priority order via OCW2.

• Edge Triggered vs. Level Triggered: Set by ICW1. Edge (LOW→HIGH transition), Level (LOW level sustained).

Initialization & Operation Command Words

• ICW1 (Mandatory): D4=1 for ICW4 needed, D3=0 (level), 1 (edge), D2=0 (single), 1 (cascade), D1-D0=0.

• ICW2 (Vector Address Base): V5 V4 V3 V2 V1 V0 → Interrupt type = V5..V0 + IR. Example: 10100000B (A0H) → IR0=08H, IR1=09H, etc.

• ICW3 (Cascading): For master/slave identification (master: which IR connected to slave; slave: which IR it is on master).

• ICW4 (Mode): D4=1 (8086/88 mode), D3=0 (not buffered), D2=0 (master), D1=0 (AEOI not used), D0=0 (non-auto EOI).

• OCW1 (IMR): 1 masks corresponding IR.

• OCW2 (EOI/Priority): D5-D3=000 for non-specific EOI, D5-D3=001 for non-specific EOI with rotate, etc.

• OCW3 (Special Mask/Read): D4-D3=00 for read IRR, 01 for read ISR, 10 for poll command.

Interrupt Sequence (8086)

1. Interrupt request (IRx) goes HIGH.

2. 8259A sends INT to CPU.

3. CPU finishes current instruction, sends INTA.

4. 8259A places interrupt type (e.g., 08H for IR0) on data bus during second INTA.

5. CPU reads type, calculates vector address = type × 4, fetches CS:IP from that location.

Cascading for 64-Level Interrupts

• One master 8259A, up to 8 slave 8259As.

• Master’s IR2–IR7 connected to slaves’ INT outputs.

• Master’s ICW3 sets bits for connected slaves.

• Slaves’ ICW3 set to their master’s IR number.

V. PROGRAMMABLE INTERVAL TIMER (8253/8254)

Block Diagram & Internal Architecture

• Data Bus Buffer: 8-bit interface.

• Read/Write Logic: Decodes CS#, RD#, WR#, A0, A1.

• Control Word Register: Written with control word.

• Counters (0,1,2): Each 16-bit down counter with mode setting, gate input, clock input, output.

• Status Buffer (8254 only): Read-back capability.

Operating Modes

• Mode 0: Interrupt on Terminal Count: Output goes HIGH after count reaches 0. GATE=1 enables counting.

• Mode 1: Hardware Retriggerable One-Shot: GATE LOW→HIGH triggers one count cycle. Output goes LOW during count, HIGH after TC.

• Mode 2: Rate Generator: Periodic square wave. Count reloaded after TC. Output HIGH for (N–1) clocks, LOW for 1 clock. Used for baud rate generation.

• Mode 3: Square Wave Generator: Similar to Mode 2 but symmetrical (50% duty cycle if even count). Output HIGH/LOW each for N/2 clocks.

• Mode 4: Software Triggered Strobe: Output goes LOW for one clock after count reaches 0. Triggered by writing count.

• Mode 5: Hardware Triggered Strobe: Like Mode 4 but triggered by GATE pulse.

Control Word Format

D7 D6 | D5 D4 | D3 D2 D1 D0
---------------------------

RW1 RW0 | Select Counter | Mode | BCD/Binary
00= latch, 01= read/write LSB, 10= read/write MSB, 11= read/write LSB then MSB
00=counter0, 01=counter1, 10=counter2, 11=read-back (8254)
000=0, 001=1, 010=2, 011=3, 100=4, 101=5
0=16-bit binary, 1=BCD (4-digit)

Interfacing with 8086

• Connect D0–D7 to data bus. Use A0, A1 to select counter/control.

• Example Port Addresses: Counter0=08H, Counter1=0AH, Counter2=0CH, Control=0EH.

• Programming: Write control word → write count (LSB then MSB or vice versa based on RW bits).

• Read: Write control word with RW=01/10 → read LSB/MSB.

Applications

• Waveform generation (Modes 2, 3).

• Event counting (Mode 0).

• Baud rate generation for USART (Mode 2).

• Time delay generation.

VI. DMA CONTROLLER (8257)

Block Diagram & Pin Diagram

• Data Bus Buffer: 8-bit bidirectional.

• Read/Write Logic: Decodes CS#, RD#, WR#, A0–A3.

• Address Register (4 channels × 16-bit): Holds memory address for transfer.

• Word Count Register (4 channels × 16-bit): Number of words to transfer. Decrements to 0.

• Control/Status Register: Contains mode bits (auto-initialize, channel priority), TC bits (terminal count status).

• Priority Encoder: Resolves channel priority (fixed or rotating).

• Control Logic: Generates HOLD, receives HLDA, generates memory/I/O addresses and control signals (MEMR#, MEMW#, IOR#, IOW#).

• Pins: HRQ (HOLD request to CPU), HLDA (Hold acknowledge), DREQ0–3 (DMA request), DACK0–3 (DMA acknowledge), IOW#, IOR#, MEMW#, MEMR#.

Register Organization

• Each channel has:

  • Address Register (AR): 16-bit memory address.

  • Word Count Register (WCR): 16-bit count.

• Command Register (CR): D0=channel 0 enable, D1=ch1 enable, D2=ch2 enable, D3=ch3 enable, D4=fixed priority (0)/rotate (1), D5=auto-initialize, D6=memory-to-I/O (0)/I/O-to-memory (1), D7=extend write (0)/read (1).

• Status Register (SR): D0–D3=TC for ch0–ch3, D4–D7=unused/read-only.

DMA Transfer Cycle (HOLD/HLDA Handshake)

1. Peripheral asserts DREQx to 8257.

2. 8257 asserts HRQ to CPU.

3. CPU completes current bus cycle, floats bus, asserts HLDA.

4. 8257 takes control, outputs address from AR, asserts MEMR#/IOR# (read) or MEMW#/IOW# (write).

5. Data transferred. AR incremented/decremented, WCR decremented.

6. If WCR ≠ 0, repeat. If WCR = 0, TC bit set in SR, DACKx goes inactive. If auto-initialize, AR/WCR reloaded from base registers.

7. 8257 deasserts HRQ. CPU reasserts bus control.

Operating Modes

• Fixed Priority: Channel 0 > 1 > 2 > 3.

• Rotating Priority: After a channel completes, its priority becomes lowest (round-robin).

Programming & Initialization Example (2KB Transfer)

• Given: Transfer 2KB (2048 bytes) from memory 75000H to I/O port via channel 1. Port addresses: 70H (8257), 80H (I/O data).

• Steps:

  1. Write Command Word to port 70H: 10000000B (ch1 enable, rotate priority, I/O-to-memory? Adjust based on direction).

  2. Write MSB of address (75H) to 70H? No—address loaded via separate ports. Typically: Address loaded via data bus during write cycle. Better: Load AR1 with 75000H via I/O write sequence (MSB first or LSB first based on mode).

  3. Write Word Count (2048 = 0800H) to WCR1.

  4. Peripheral asserts DREQ1.

  5. 8257 performs DMA cycles: Read memory (MEMR#), write I/O (IOW# to 80H).

VII. COMMUNICATION INTERFACE: USART (8251)

Block Diagram & Functional Units

• Transmitter: Parallel-to-serial converter, shift register, parity generator. Output TXD.

• Receiver: Serial-to-parallel converter, shift register, parity checker, overrun/error detection. Input RXD.

• Baud Rate Generator: Generates clock from external RxC/TxC or internal (from CLK).

• Control/Status Logic: Handles mode/command programming, status read, interrupts.

• Data Bus Buffer: 8-bit interface.

• Pins: CS#, WR#, RD#, C/D (control/data select), TXD, RXD, TxC, RxC, TxRDY, RxRDY, SYNDET, DTR, RTS, CTS.

Control Word Format

• Mode Instruction (C/D=1, WR=0):

  
  D7 D6 | D5 | D4 D3 | D2 D1 D0
  
  ----------------------------
  
  Baud Factor | Sync/Async | Character Size | Parity
  
  00=1, 01=16, 10=64 (async baud factor)
  
  0=async, 1=sync
  
  00=5 bits, 01=6, 10=7, 11=8
  
  0=no parity, 1=odd parity (D7=0), even parity (D7=1)
  
  

  For sync mode: D5=1, D4-D0 define sync character (if needed).

• Command Instruction (C/D=1, WR=0):

  
  D7 D6 | D5 | D4 | D3 | D2 | D1 | D0
  
  --------------------------------
  
  Tx Enable | DTR | TxRDY | Rx Enable | RTS | RxRDY | SBRK
  
  1=enable transmitter
  
  1=DTR active
  
  1=TxRDY active (data needed)
  
  1=enable receiver
  
  1=RTS active
  
  1=RxRDY active (data ready)
  
  1=send break (TXD=LOW)
  
  

Status Word Format & Interpretation

• Read with C/D=1, RD=0.

  
  D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0
  
  --------------------------------
  
  TxEMT | TxRDY | RxRDY | OE | PE | FE | SBD | DCD
  
  

  • TxEMT: Transmitter empty (shift register & buffer empty).

  • TxRDY: Transmitter ready for data (buffer empty).

  • RxRDY: Receiver ready (data in buffer).

  • OE: Overrun error (new data before reading old).

  • PE: Parity error.

  • FE: Framing error (stop bit not 1).

  • SBD: Sync break detect (async mode).

  • DCD: Data carrier detect (modem).

Interfacing for Serial Communication

• Connect TXD/RXD to RS-232 level shifter (MAX232).

• Connect TxC/RxC to clock source (external or internal from CLK).

• Connect CTS/RTS for modem handshaking.

• 8086 Interface: IN/OUT instructions. Use C/D pin to select data (0) or control/status (1). Example: Port address 00H (data), 02H (control/status).

VIII. A/D AND D/A CONVERTER INTERFACING

ADC (0808/0809)

• Block Diagram: 8-channel multiplexer, sample-hold, comparator, successive approximation register/DAC, control logic.

• Control Signals:

  • START: Rising edge starts conversion.

  • EOC (End of Conversion): Goes LOW during conversion, HIGH when done.

  • ALE: Locks address (channel select) on rising edge.

  • OC (Output Enable): Enables output tri-state buffers.

  • CLK: Clock input (typically 640kHz max).

• Interfacing with 8086:

  1. Output channel address (0–7) to address lines A0–A2. Use OUT to latch via ALE.

  2. Pulse START (short HIGH pulse).

  3. Poll EOC (input via port) or use interrupt.

  4. When EOC=HIGH, read data byte via IN (with OC=LOW).

  Example: Channel address on port 00H, control port 02H (START bit), status port 04H (EOC bit).

DAC (0800/0832)

• 0800: 8-bit current output DAC. Requires external op-amp for voltage output.

• 0832: 8-bit dual DAC (two channels). Current output.

• Interfacing:

  • Connect data bus to DAC inputs.

  • Use CS# (chip select), WR# (write strobe) to latch data.

  • For 0832, use A0 to select channel.

  • 8086: OUT port, AL writes data to DAC. Output analog voltage proportional to digital value.

IX. 8051 MICROCONTROLLER

Architecture & Block Diagram

• CPU: 8-bit ALU, accumulator (A), B register, PSW, program counter (PC), stack pointer (SP), data pointer (DPTR).

• Internal Memory:

  • RAM: 128 bytes (8051) / 256 bytes (8052). Lower 32 bytes: 4 register banks (R0–R7). Upper 128 bytes: SFRs (if 256-byte RAM).

  • ROM: 4KB (8051) / 8KB (8052). Holds program & constants.

  • SFR Map: 80H–FFH (128 bytes). Includes ports, timers, SCON, etc.

• I/O Ports:

  • Port 0: Dual function. As I/O: open-drain, needs pull-ups. As address/data bus (AD0–AD7) when accessing external memory.

  • Port 1: Pure I/O (quasi-bidirectional, internal pull-up).

  • Port 2: Dual function. As I/O: quasi-bidirectional. As high-order address bus (A8–A15) for external memory.

  • Port 3: Dual function. Pins have alternate functions:

    | Pin | Alternate Function | | :--- | :--- | | P3.0 | RXD (serial input) | | P3.1 | TXD (serial output) | | P3.2 | INT0 (external interrupt 0) | | P3.3 | INT1 (external interrupt 1) | | P3.4 | T0 (timer 0 external input) | | P3.5 | T1 (timer 1 external input) | | P3.6 | WR# (external memory write) | | P3.7 | RD# (external memory read) |

• Timers/Counters (T0, T1):

  • TMOD (Timer Mode): GATE C/T M1 M0 for each timer.

    • M1 M0: 00=Mode0 (13-bit timer), 01=Mode1 (16-bit), 10=Mode2 (8-bit auto-reload), 11=Mode3 (T0 split, T1 stopped).

    • C/T: 0=timer (internal clock), 1=counter (external pulses on T0/T1).

    • GATE: 1=timer enabled only when INT0/INT1 pin HIGH.

  • TCON (Timer Control): TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0.

    • TFx: Timer overflow flag (set by hardware, cleared by software).

    • TRx: Timer run control (1=start).

    • IEx: Interrupt edge flag (0=level, 1=falling edge).

    • ITx: Interrupt type (0=level, 1=transition).

• Serial Communication (UART):

  • SBUF: Serial data buffer (read for receive, write for transmit).

  • SCON (Serial Control): SM0 SM1 SM2 REN TB8 RB8 TI RI.

    • SM0 SM1: Mode 0 (shift register), 1 (8-bit UART, baud rate fixed), 2 (9-bit UART, baud rate = fosc/32), 3 (9-bit UART, baud rate variable).

    • SM2: Enable multiprocessor communication (Mode 2/3).

    • REN: Receive enable (1=enable).

    • TB8/RB8: 9th bit for transmit/receive.

    • TI: Transmit interrupt flag (set after stop bit, cleared by software).

    • RI: Receive interrupt flag (set after stop bit, cleared by software).

  • PCON (Power Control): SMOD (double baud rate in Mode 1/3 if set).

Addressing Modes (8051-specific)

Interrupt Structure

• Sources & Vector Addresses:

  | Source | Flag | Vector Address | | :--- | :--- | :--- | | External 0 | IE0 | 0003H | | Timer 0 | TF0 | 000BH | | External 1 | IE1 | 0013H | | Timer 1 | TF1 | 001BH | | Serial | RI/TI | 0023H |

• Enable Register (IE): EA (global enable), ES (serial), ET1 (timer1), EX1 (ext1), ET0 (timer0), EX0 (ext0).

• Priority Register (IP): PS, PT1, PX1, PT0, PX0 (1=high priority).

• Priority: High-priority interrupts can preempt low-priority. Same priority: natural order (IE0, TF0, IE1, TF1, RI/TI).

Special Function Registers (SFRs) - Key

Pin Diagram & Functions

• VCC, GND: Power.

• XTAL1, XTAL2: Crystal oscillator connections.

• RST: Reset input (active HIGH, >2 machine cycles).

• ALE: Address Latch Enable (outputs pulse at 1/6 oscillator freq). Latches low byte of address from P0.

• PSEN: Program Store Enable (read from external ROM).

• EA/VPP: External Access (0=external program memory, 1=internal). VPP for EPROM programming.

• P0.0–P0.7: Dual function (AD0–AD7 / I/O).

• P1.0–P1.7: Pure I/O.

• P2.0–P2.7: Dual function (A8–A15 / I/O).

• P3.0–P3.7: Dual function (I/O / alternate functions as listed above).

Programming Examples

• Rotate/Swap:

  • RL A (rotate left through carry? No, RL is rotate left within accumulator).

  • RLC A (rotate left through carry).

  • SWAP A (swap nibbles: A[7:4] ↔ A[3:0]).

• Stack Operation:

  
  MOV SP, #60H    ; Set stack top
  
  MOV R1, #11H
  
  MOV R2, #22H
  
  MOV R3, #33H
  
  PUSH 1          ; Push R1 (address 00H? No, PUSH direct address)
  
  PUSH 2          ; Push R2
  
  PUSH 3          ; Push R3
  
  ; Stack: 60H=11H, 61H=22H, 62H=33H, SP=63H
  
  

X. ADVANCED PROCESSORS & EMBEDDED SYSTEMS

RISC vs. CISC

Intel 80x86 Family Evolution

• 80286: 16-bit, 24-bit address (16MB), protected mode (memory protection, multitasking), new instructions (PUSH/POP all regs, bounds check).

• 80386: 32-bit registers/address bus (4GB), paging, virtual 8086 mode, task switching, 3 operating modes (real, protected, virtual).

• 80486: On-chip 8KB cache, pipelined (5-stage), integrated FPU, burst bus cycles.

• Pentium: Superscalar (U & V pipes), separate code/data caches (8KB each), branch prediction, 64-bit data bus, dual-port cache.

Embedded Systems

• Definition: Specialized computer system designed for specific tasks, often with real-time constraints, embedded in larger device.

• Classification:

  • Based on Performance: Low-end (4-bit/8-bit), mid-range (16-bit), high-end (32-bit/64-bit).

  • Based on Complexity: Simple (single-chip), complex (multi-processor, OS).

  • Based on Functionality: Standalone, real-time, networked, mobile.

• Role of Microcontrollers: Core processing unit in embedded systems. Integrates CPU, memory, I/O, timers, ADC/DAC, communication interfaces on single chip. Reduces cost, size, power.

XI. FREQUENTLY ASKED COMPARISONS & CONCEPTS

BSR Mode vs. I/O Mode (8255)

Memory-Mapped I/O vs. I/O-Mapped I/O

Interrupt-Driven I/O vs. DMA

Hardware vs. Software Interrupts

• Hardware Interrupts (8086): External pins INTR (maskable), NMI (non-maskable). Generated by peripherals.

• Software Interrupts (8086): INT n instruction (e.g., INT 21H for DOS). INT3 (breakpoint).

• 8051: Hardware: INT0, INT1 (P3.2, P3.3). Software: ACALL/LCALL to interrupt vector? No—8051 has no software interrupt instruction. External events or timer/serial flags trigger.

On-chip vs. Off-chip ROM Access (8051)

• EA# Pin: EA# = 1 → internal ROM (0000H–0FFFH) used first, then external if address > 0FFFH. EA# = 0 → external ROM only (0000H–FFFFH).

• PSEN Signal: Active when fetching from external program memory (when EA#=0 or address > 0FFFH with EA#=1). Not used for internal ROM access.

Exam Tips:

• Timing Diagrams: Always label T-states, signals (ALE, RD#, etc.), and data/address validity.

• Addressing Modes: Know effective address calculation for each 8086 mode. For 8051, distinguish direct (8-bit address) vs. indirect (@Ri).

• Peripheral Programming: Practice writing control words for 8255, 8253, 8259A. Know port addresses and read/write sequences.

• 8051 SFRs: Memorize key addresses (PSW=0D0H, ACC=0E0H, P0=80H, etc.) and bit positions (PSW bits: CY, AC, F0, RS1, RS0, OV, -).

• Comparisons: Use tables in answers for clarity (RISC/CISC, I/O modes).

• Programming: For sorting/frequency, use simple loops with LOOP or DEC CX/JNZ. For string ops, set SI/DI, CX, and use REP prefix.