UNIT 4: MICROPROCESSOR & APPLICATIONS - EXAM-FOCUSED NOTES

(Based on RGPV EC-501 Past Papers 2022-2025)

I. 8086 MICROPROCESSOR FUNDAMENTALS

Architecture & Organization

• Functional Blocks:

  • BIU (Bus Interface Unit): Fetches instructions, calculates physical addresses, manages bus cycles.

  • EU (Execution Unit): Decodes/executes instructions, operates on registers.

  • Segmentation: 64KB segments (CS, DS, SS, ES) → 1MB address space via segment:offset.

• Register Organization:

  | Type | Registers | Purpose | |----------------|----------------------------------------|--------------------------------------| | General | AX, BX, CX, DX | 16-bit data/address operations | | Segment | CS, DS, SS, ES | Segment base addresses | | Pointer/Index | SP, BP, SI, DI | Stack, base, source, index | | Flag | FLAGS (16-bit) | Status & control flags |

• Flag Register (Key Flags):

  • CF (Carry): Unsigned overflow

  • ZF (Zero): Result = 0

  • SF (Sign): MSB = 1 (negative)

  • PF (Parity): Even # of 1s in LSB

  • AF (Aux Carry): Carry from bit 3 to 4 (BCD)

  • OF (Overflow): Signed overflow

  • TF (Trap): Single-step debugging

  • IF (Interrupt): Enable/disable INTR

  • DF (Direction): String ops increment (0) / decrement (1)

Operating Modes

Timing Diagrams (Key States)

• Memory Read Cycle (Min Mode):

  T1: ALE high → latch address (AD0–AD15 → A0–A19). M/IO# = 1 (memory).

  T2: RD# low, AD bus floated, DT/R = 1 (read), DEN enabled.

  T3: Data valid on bus, read by EU.

  T4: RD# high, cycle ends.

  [!TIP] For LXI H, 5000H: 4 machine cycles (opcode fetch + 2 memory reads + 1 internal). For MVI A, FFH: 2 cycles (opcode fetch + internal).

• Memory Write Cycle: Similar but WR# low, DT/R = 0 (write), data driven by 8086 in T2–T3.

Memory Organization

• Physical Address Calculation:

$$\text{Physical Address} = (\text{Segment Register} \times 16) + \text{Offset}$$

Example: CS:IP = 2000H:0100H → 20000H + 0100H = 20100H.

• Even/Odd Bank:

  • Even bank (A0 = 0): D0–D7 → even addresses, D8–D15 → odd addresses.

  • Word access: A0 = 0 → both banks active; A0 = 1 → only odd bank (byte access).

• Segmentation Advantages:

  • Allows >64KB programs via multiple segments.

  • Code/data/stack separation → protection & modularity.

II. 8086 PROGRAMMING MODEL & INSTRUCTION SET

Addressing Modes (High Frequency)

Instruction Set Categories (Key Instructions)

• Data Transfer: MOV, PUSH/POP (stack ops), XCHG, IN/OUT (I/O), LEA (load effective address), LDS/LES (load far pointer).

• Arithmetic: ADD/ADC (with carry), SUB/SBB (with borrow), INC/DEC, MUL/IMUL (unsigned/signed), DIV/IDIV, AAA/AAS (ASCII adjust), DAA/DAS (BCD adjust).

• Logical: AND, OR, XOR, NOT, TEST (and set flags), shifts/rotates: SHL/SAL (<<), SHR (>> logical), SAR (>> arithmetic), ROL/ROR, RCL/RCR (through carry).

• Branch/Transfer: JMP (unconditional), CALL/RET (near/far), LOOP (CX–), JCXZ (jump if CX=0), conditional jumps (JE, JNE, JL, JG, etc.).

• Flag Manipulation: STC/CLC (carry), STD/CLD (direction), STI/CLI (interrupt), PUSHF/POPF.

• String Operations: MOVSB/MOVSW (move), CMPSB (compare), SCASB (scan), LODSB (load), STOSB (store) with REP prefix.

Assembly Programming (Examples)

1. Sorting (Ascending):

   
   ; Assume N=4, array at [SI]
   
   MOV CX, 3          ; Outer loop count (N-1)
   
   OUTER: MOV DI, SI
   
          MOV DX, CX
   
   INNER: MOV AX, [DI]
   
          CMP AX, [DI+2]
   
          JBE SKIP
   
          XCHG AX, [DI+2]
   
          MOV [DI], AX
   
   SKIP:  INC DI
   
          INC DI
   
          DEC DX
   
          JNZ INNER
   
          LOOP OUTER
   
   

2. Frequency Count of Byte BH in Array:

   
   MOV SI, OFFSET ARRAY  ; SI = start address
   
   MOV CX, N             ; N elements
   
   XOR AL, AL            ; Count = 0
   
   BACK: CMP [SI], BH
   
         JNE NEXT
   
         INC AL
   
   NEXT: INC SI
   
         LOOP BACK
   
   MOV RESULT, AL
   
   

3. Clear Lower 4 Bits of BL: AND BL, 0F0H → preserves upper nibble.

III. MEMORY & I/O INTERFACING

Memory Interfacing

• Address Decoding:

  • Absolute: Full address decoded → unique chip select (e.g., A0–A15 → 1 chip).

  • Partial: Some address lines ignored → multiple addresses map to same chip (reduces hardware, may cause aliasing).

• Memory Map Example (32KB RAM + 2×4KB EPROM):

  • EPROM 1: 00000H–00FFFH (4KB) → CS0 = A15=A14=...=A12=0?

  • EPROM 2: 01000H–01FFFH (4KB) → CS1 = A15=0, A14=1, others=0?

  • RAM: 20000H–27FFFH (32KB) → CS_RAM = A15=1, A14=0? (Use 74LS138 decoder).

• Chip Select Logic:

$$\text{CS} = \overline{A_{15}} \cdot \overline{A_{14}} \cdot A_{13} \cdot \overline{A_{12}}$$

(example for 4KB block).

• Even/Odd Bank Interfacing: Connect A0 to BHE# (Bus High Enable). For word access: A0=0 → both banks; A0=1 → only odd bank (byte).

I/O Interfacing

8255A PPI (High Frequency)

• Pin Diagram: PA0–PA7, PB0–PB7, PC0–PC7, RD#, WR#, CS#, A0–A1, Vcc/GND.

• Modes:

  • Mode 0 (I/O): Simple input/output, no handshake.

    Control Word format:

    1 (mode set) + D4 D3 (PA mode) + D2 (PA I/O) + D1 (PB mode) + D0 (PB I/O) + PC split (upper/lower).

    BSR mode: 0 (BSR) + D3–D1 (PC bit) + D0 (set/reset).

  • Mode 1 (Strobe I/O): Handshake using PC lines (e.g., Port A output: PC3=OBF#, PC4=ACK#, PC5=INTEA).

  • Mode 2: Bidirectional bus (Port A only).

• Interfacing Example (8086-8255):

  • Low byte (D0–D7) → connect to 8255 data bus.

  • Address decoding: CS = A15·A14·A13·A12·A11·A10·A9·A8·A7·A6·A5·A4·A3·A2·A1·A0? (Use partial decoding: e.g., A9–A0 = 00H–06H for ports).

  • I/O addresses: Port A=00H, Port B=02H, Port C=04H, Control=06H.

IV. PROGRAMMABLE PERIPHERALS & INTERFACING ICs

8253/8254 PIT (High Frequency)

• Block Diagram: 3 independent 16-bit counters (0,1,2), control word register, read/write logic.

• Modes of Operation:

  | Mode | Name | Trigger | Output | |----------|----------------------------|-------------|-------------------------------------| | 0 | Interrupt on Terminal Count| Software | Low until count=0, then high | | 1 | Hardware Retriggerable One-Shot | Hardware | Pulse width = count × clock period | | 2 | Rate Generator | Software | Periodic square wave (count/2 high, count/2 low) | | 3 | Square Wave Generator | Software | Symmetrical square wave (like Mode 2 but 50% duty) | | 4 | Software Triggered Strobe | Software | Low for 1 clock after count=0 | | 5 | Hardware Triggered Strobe | Hardware | Low for 1 clock after count=0 & trigger |

• Control Word Format:

  1 (select counter) + D5–D4 (read/load) + D3–D1 (mode) + D0 (BCD/binary).

  Example: Counter 0, Mode 3, binary, write LSB then MSB → 36H.

• Square Wave Generation (Mode 3) Flowchart:

  1. Load control word (e.g., 36H).

  2. Load count (e.g., 1000H).

  3. Output toggles when count decrements to 0 → reload → repeat.

  4. Frequency = Clock / Count.

• 8086 Interfacing: I/O port addresses (e.g., Counter0=08H, Control=0EH). Use OUT to write control word, then count.

8257 DMA Controller (High Frequency)

• Register Organization:

  • 4 Channels: Each has 16-bit Address Register (source/dest) + 16-bit Word Count Register.

  • Command Register: Enable channels, fixed/rotate priority, memory→I/O/I/O→memory, address increment/decrement.

  • Status Register: Terminal Count (TC) flags for channels.

  • Mask Register: Mask channels (1=masked).

  • Temporary Register: Holds data during memory-to-memory transfer.

• DMA Transfer Cycle:

  1. Fetch: DMA gets control (HOLD/HLDA).

  2. Active: Transfer byte/word (read from source, write to dest).

  3. Idle: Wait for next request.

• Initialization Example (2KB Transfer):

  • Source memory: 75000H, dest I/O (channel 1), 2KB = 0800H words.

  • Channel 1 Address Reg = 75000H, Word Count = 0800H.

  • Command Reg: CH1 enable, memory→I/O, increment memory.

  • I/O port addresses: Channel 0–3 = 70H–73H (address), 74H–77H (count), 78H (command), 79H (status), 7AH (mask), 7BH (temp).

8259A PIC (High Frequency)

• Block Components:

  • IRR (Interrupt Request Register): Latches pending interrupt requests (IR0–IR7).

  • ISR (In-Service Register): Tracks interrupts being serviced.

  • Priority Resolver: Determines highest priority IR (fixed/rotate).

  • IMR (Interrupt Mask Register): Masks interrupts (1=masked).

  • Control Logic: Generates INT to CPU, handles cascading.

• Modes:

  • Fully Nested: Fixed priority (IR0 highest).

  • Automatic Rotation: After ISR, next highest priority becomes highest.

  • Specific Rotation: Rotate to specific IR.

  • Edge/Level Triggered: Configurable via ICW.

  • Call Address Interval: 8086 mode (ICW1 bit 3 = 1 → 4-byte call address).

• ICWs/OCWs:

  • ICW1: Start initialization, edge/level, single/cascade, call address interval.

  • ICW2: Vector base address (e.g., 08H → IR0 vector = 08H).

  • ICW3: Cascading (master/slave IDs).

  • ICW4: 8086 mode, auto/normal EOI, buffer mode.

  • OCW1: Mask bits (IMR).

  • OCW2: EOI, rotate commands.

  • OCW3: Read IRR/ISR, poll command.

8251 USART (High Frequency)

• Block Diagram: Transmitter (parallel→serial), Receiver (serial→parallel), Data Buffer, Control Logic.

• Control Word Format:

  • Mode Instruction: Sync/async, baud rate factor, character length (5–8 bits), parity (even/odd/1/0).

    Example: Async, 7-bit, even parity, 1 stop bit → 1EH? (Check datasheet).

  • Command Instruction: Transmit/Receive enable, DTR, RTS, SBRK (break).

  • Status Word:

    | Bit | Name | Meaning | |---------|----------|---------------------------------| | D0 | TxRDY | Transmitter ready (buffer empty)| | D1 | RxRDY | Receiver ready (data available)| | D2 | TXE | Transmitter empty (shift reg) | | D3 | PE | Parity error | | D4 | OE | Overrun error | | D5 | FE | Framing error | | D6–D7 | – | Always 0 |

• Serial Interfacing with 8086: Connect data bus to 8251 D0–D7, use I/O addresses for control/data ports. Connect TxD/RxD to RS-232 level shifter (MAX232).

ADC & DAC Interfacing (High Frequency)

• 0808/0809 ADC (8-bit, 8-channel):

  • Control Signals:

    • START: Rising edge → start conversion.

    • EOC: High → conversion complete.

    • ALE: Latch channel address (ADDA–ADDC).

    • OE: Output enable (read data).

  • Interfacing Steps:

    1. Output channel address to ADDA–ADDC (via 8255 or latch).

    2. Pulse START (short high).

    3. Wait for EOC = 1 (polling or interrupt).

    4. Set OE = 1, read data from D0–D7.

• DAC0800 (8-bit):

  • Input: 8-bit parallel data (D0–D7).

  • Control: CS, WR (latch data on falling edge).

  • Output: Current I_out = (V_ref × Data)/256.

  • Voltage Conversion: Use op-amp (I→V converter).

  • Interfacing: Connect data bus to DAC, use I/O port for CS/WR.

V. 8051 MICROCONTROLLER

Architecture & Pin Diagram (High Frequency)

Memory Organization

• Program Memory:

  • EA=1: Internal ROM (0000H–0FFFH) first, then external (if addressed).

  • EA=0: Only external ROM (PSEN active).

  • Sequence: PC → P2 (A8–A15), P0 (AD0–AD7) latched by ALE → PSEN low → read.

• Data Memory:

  • Internal RAM: 00H–7FH (128 bytes), 80H–FFH (SFRs).

  • External RAM: Up to 64KB via MOVX (P0/P2 as address/data).

  • SFR Space: 80H–FFH (special function registers).

Special Function Registers (SFRs) (High Frequency)

Addressing Modes (High Frequency)

Instruction Set Highlights

• Data Transfer: MOV (reg/imm/direct/indirect), MOVC (code memory), MOVX (external RAM), PUSH/POP (stack), XCH/XCHD (nibble swap).

• Arithmetic: ADD/ADDC/SUBB, DA (BCD adjust), INC/DEC, MUL/DIV (A×B→BA, AB÷B→A=quot, B=rem).

• Logical: ANL/ORL/XRL (reg, direct, immediate), CLR/CPL (bit/accumulator).

• Branch: JZ/JNZ (A=0?), CJNE (compare & jump if ≠), DJNZ (decrement & jump), ACALL/LCALL/RET/RETI.

• Rotate/Swap: RL/RLC (left), RR/RRC (right), SWAP (swap nibbles of A).

Interrupt Structure (High Frequency)

• Sources:

  • External: INT0 (P3.2, vector 0003H), INT1 (P3.3, vector 0013H).

  • Timer: TF0 (000BH), TF1 (001BH).

  • Serial: RI/TI (0023H).

  • Software: TRAP (non-maskable, 0023H? Actually 0023H is serial; TRAP is 0023H? Correction: TRAP vector = 0023H? Standard: INT0=0003H, INT1=0013H, T0=000BH, T1=001BH, Serial=0023H, TRAP=0023H? Actually TRAP is same as serial? No: 8051 vectors: 0000H (reset), 0003H (INT0), 000BH (T0), 0013H (INT1), 001BH (T1), 0023H (Serial), 002BH (T2? Not in 8051). TRAP is same as INT0? Actually 8051 has 5 interrupt sources: INT0, T0, INT1, T1, Serial. TRAP is not separate; it's a non-maskable version of INT0? Correction: 8051 has 5 interrupt sources with fixed vectors. TRAP is not a separate pin; it's a software instruction? Actually TRAP is a software interrupt (opcode) but mapped to vector 0023H? No: TRAP is opcode C4H (same as JNB? Wait). Standard 8051 interrupt sources:

    1. INT0 (P3.2) → 0003H

    2. T0 (TF0) → 000BH

    3. INT1 (P3.3) → 0013H

    4. T1 (TF1) → 001BH

    5. Serial (RI/TI) → 0023H

    There is also TRAP (opcode C4H) which is a non-maskable interrupt (NMI) but not in original 8051? Actually 8051 has TRAP as a non-maskable interrupt on vector 0023H? I think TRAP is a software interrupt instruction (like INT in x86) but 8051 doesn't have software interrupts except ACALL to ISR? Correction: 8051 has RST0–RST7 (software interrupts) at vectors 0000H, 0008H, 0010H, ..., 0038H. But TRAP is not standard. Let's clarify:

    • Hardware Interrupts: INT0, INT1, T0, T1, Serial.

    • Software Interrupts: RST n (n=0–7) → push PC, jump to n×8.

    • Non-Maskable: INT0 can be edge/level triggered; if level, it's like NMI? Actually TRAP is not in 8051; it's in 8085. For 8051, we have:

      • External 0 (INT0) – can be edge/level (IT0 bit).

      • External 1 (INT1) – IT1 bit.

      • Timer 0 (TF0).

      • Timer 1 (TF1).

      • Serial (RI/TI).

      • RST pins? No, RST is reset.

    So stick to 5 hardware interrupts.

  • Priority: Natural (fixed): INT0 > T0 > INT1 > T1 > Serial. Programmable via IP register (bit=1 → high priority).

• Interrupt Response Sequence:

  1. CPU finishes current instruction.

  2. Clears corresponding flag (TF? RI/TI? Actually hardware clears TF0/TF1/RI/TI automatically? No: TF0/TF1 cleared by hardware when ISR executed? Actually they are cleared by hardware when ISR is called? Correction: TF0/TF1 are cleared by hardware when ISR is executed? No, they are flags in TCON; software must clear them? Actually for 8051, hardware clears the interrupt flag when ISR is called? Let's check: For timer interrupts, TF0/TF1 are cleared by hardware when ISR is executed? Actually in 8051, the interrupt flags (TF0, TF1, RI, TI) are not cleared by hardware automatically; software must clear them in ISR. But the interrupt request is cleared by hardware when ISR starts? The process:

     • Interrupt occurs → flag set (TF0, RI, etc.) → if enabled (IE) and not masked (IP), CPU finishes current instruction, pushes PC, clears corresponding flag? Actually the flag (TF0) remains set until cleared by software. The interrupt request is latched in IRR? 8051 doesn't have IRR/ISR like 8259. The interrupt is recognized if flag=1 and IE bit=1. After vector fetch, the flag is not automatically cleared; software must clear it to prevent re-interrupt. But the interrupt acknowledge is implicit.

     So sequence:

     1. Interrupt condition sets flag (e.g., TF0=1).

     2. If IE.T0=1 and not higher priority interrupt active, CPU finishes current instruction.

     3. CPU pushes PC (2 bytes) onto stack.

     4. CPU fetches vector from fixed address (e.g., 000BH for T0).

     5. Jumps to ISR.

     6. Software must clear flag (e.g., CLR TF0) before RETI.

     7. RETI pops PC and restores priority.

Serial Communication

• UART Operation (Asynchronous Modes 1–3):

  • Mode 1: 8-bit UART, 1 start bit, 8 data bits, 1 stop bit (variable baud).

  • Mode 2: 9-bit UART (for multiprocessor).

  • Mode 3: 9-bit UART with variable baud.

• SFRs:

  • SCON (98H):

    | Bit | Name | Function | |-----|------|-------------------------------------------| | D0 | RI | Receive interrupt flag (set on 8th bit). | | D1 | TI | Transmit interrupt flag (set on stop bit).| | D2 | RB8 | 9th received bit (Mode 2/3). | | D3 | TB8 | 9th transmitted bit (Mode 2/3). | | D4 | REN | Receive enable (1=enable). | | D5–D6| SM0/SM1 | Mode select (00=Mode0, 01=Mode1, 10=Mode2, 11=Mode3). | | D7 | – | 0. |

  • SBUF (99H): Read (receive), write (transmit).

  • PCON (87H): SMOD (baud rate double for Timer1 mode2).

• Baud Rate Generation: Timer1 in Mode2 (8-bit auto-reload).

$$\text{Baud Rate} = \frac{\text{OSC}}{12 \times (256 - \text{TH1})} \times \text{SMOD}$$

(for Mode1/3).

I/O Ports & Alternate Functions

• Port 0: AD0–AD7 (multiplexed), need external pull-ups (10kΩ). Used for external memory access.

• Port 1: Pure I/O (internal pull-up).

• Port 2: A8–A15 (high address) for external memory, else I/O.

• Port 3 Alternate Functions:

  P3.0 = RXD (serial input),

  P3.1 = TXD (serial output),

  P3.2 = INT0 (external interrupt 0),

  P3.3 = INT1 (external interrupt 1),

  P3.4 = T0 (timer 0 external input),

  P3.5 = T1 (timer 1 external input),

  P3.6 = WR (external RAM write strobe),

  P3.7 = RD (external RAM read strobe).

VI. ADVANCED TOPICS & COMPARISONS

Processor Evolution

RISC vs. CISC (High Frequency)

Embedded Systems

• Definition: Dedicated computer system within larger device (e.g., microwave, car ECU).

• Characteristics: Real-time operation, low power, cost-sensitive, reliability.

• Classification:

  1. Standalone (e.g., calculator).

  2. Real-time (hard/soft, e.g., flight control).

  3. Networked (connected, e.g., IoT devices).

  4. Mobile (portable, e.g., smartphones).

• Role of Microcontrollers: Core processing unit (CPU + memory + I/O on single chip), low cost, low power, deterministic.

VII. FREQUENTLY ASKED SHORT NOTE TOPICS (From Past Papers)

BSR Mode vs. I/O Mode of 8255

• BSR (Bit Set/Reset) Mode:

  • Control word bit 7 = 0.

  • Used to set/reset individual bits of Port C without affecting other bits.

  • Format: 0 + 000 + D3 D2 D1 (bit select) + D0 (1=set, 0=reset).

  • Example: Set PC3 → 00001001B = 09H.

  • Use: Generate square wave on single PC pin, control individual LEDs.

• I/O Mode (Mode 0):

  • Control word bit 7 = 1.

  • Entire ports (A, B, C) configured as input/output.

  • No handshake; simple data transfer.

  • Port C can be split into upper/lower for input/output independently.

Control Word of USART (8251)

• Mode Instruction (first):

  1 (sync/async: 0=sync, 1=async) + D6 (baud rate factor: 0=×1, 1=×16/64) + D5–D4 (character length: 00=5, 01=6, 10=7, 11=8) + D3 (parity enable) + D2 (even/odd parity) + D1–D0 (stop bits: async: 00=1, 01=1.5, 10=2).

• Command Instruction (second):

  D7 (transmit enable), D6 (receive enable), D5 (DTR), D4 (RTS), D3 (SBRK), D2 (ER), D1 (RI), D0 (TI).

• Status Read: Bits D0 (TxRDY), D1 (RxRDY), D2 (TXE), D3 (PE), D4 (OE), D5 (FE).

8259A Registers: IRR, ISR, Priority Resolver

• IRR (Interrupt Request Register): 8-bit, latches pending interrupt requests (IR0–IR7). Set by external signals, cleared when interrupt acknowledged.

• ISR (In-Service Register): 8-bit, tracks interrupts currently being serviced. Bit set when interrupt acknowledged, cleared by EOI command.

• Priority Resolver: Compares IRR and ISR to determine highest priority pending interrupt (not masked, not in-service). Outputs to interrupt logic.

Memory Read Cycle Timing Diagram (8086 Min/Max Mode)

• Min Mode:

  T1: ALE=1 (latch address), M/IO#=1, RD#/WR# inactive.

  T2: ALE=0, RD#=0 (read), AD bus floated, DT/R=1 (read), DEN=1.

  T3: Data valid on bus.

  T4: RD#=1, cycle ends.

  Ready signal (RDY) can extend T3/TW.

• Max Mode: Similar but control signals (RD#, WR#) generated by 8288 bus controller; S0–S2 indicate cycle type (e.g., S2=1,S1=0,S0=1 for memory read). QS0/QS1 indicate queue status.

8051 Pin Functions

• ALE: Address Latch Enable → latches low byte of address from P0 (during T1).

• P0.0–P0.7: Multiplexed AD0–AD7 (need external pull-ups), used for address/data in external memory cycles.

• PSEN: Program Store Enable → active low during external ROM fetch.

• RST: Reset → high for ≥2 machine cycles (24 oscillator periods) initializes microcontroller (SP=07H, PC=0000H, ports=FFH).

8254 Timer Modes (Focus Mode 3 – Square Wave)

• Mode 3 (Square Wave Generator):

  • Count is loaded into counter.

  • Output high for first half of count, low for second half.

  • When count reaches 0, reloaded automatically → periodic square wave.

  • Frequency = Clock / Count.

  • Used for baud rate generation, tone generation.

8257 DMA Register Organization

• Channel Registers (×4):

  • DMA Address Register (16-bit): Source/dest memory address.

  • DMA Word Count Register (16-bit): Number of transfers (N).

• Command Register (8-bit): Enable channels, memory→I/O/I/O→memory, address increment/decrement, priority (fixed/rotate).

• Status Register (8-bit): TC bits (one per channel), error bits.

• Mask Register (8-bit): Mask channels (1=masked).

• Temporary Register (8-bit): Holds data during memory-to-memory transfer.

8051 SFRs (ACC, PSW, SCON, TCON)

• ACC (0E0H): Accumulator, used in arithmetic/logical ops, result storage.

• PSW (0D0H):

  | Bit | Name | Function | |-----|------|-----------------------------------| | D7 | CY | Carry flag | | D6 | AC | Auxiliary carry (BCD) | | D5 | F0 | User flag | | D4–D3| RS1–RS0 | Register bank select (0–3) | | D2 | OV | Overflow flag | | D1 | – | 0 | | D0 | P | Parity (even=1) of accumulator |

• SCON (98H): Serial control (see table in Section V).

• TCON (88H):

  | Bit | Name | Function | |-----|------|-----------------------------------| | D7 | TF1 | Timer1 overflow flag | | D6 | TR1 | Timer1 run control (1=start) | | D5 | TF0 | Timer0 overflow flag | | D4 | TR0 | Timer0 run control | | D3 | IE1 | External interrupt 1 edge flag | | D2 | IT1 | External interrupt 1 type (0=level,1=edge) | | D1 | IE0 | External interrupt 0 edge flag | | D0 | IT0 | External interrupt 0 type |

8051 Interrupts (Hardware vs. Software, Priority)

• Hardware Interrupts: INT0 (P3.2), INT1 (P3.3), T0 (TF0), T1 (TF1), Serial (RI/TI).

• Software Interrupts: RST n (n=0–7) → vectors at n×8 (e.g., RST0=0000H, RST1=0008H, ..., RST7=0038H).

• Priority:

  • Natural (Fixed): INT0 > T0 > INT1 > T1 > Serial.

  • Programmable: IP register bits (PS, PT1, PX1, PT0, PX0). 1=high priority, 0=low.

  • Rules: High-priority interrupt can preempt low-priority; same priority handled by natural order; RETI returns to interrupted point.

ADC & DAC Interfacing Basics

• ADC (0808/0809):

  • 8-bit, 8-channel multiplexer.

  • Interfacing Steps:

    1. Output channel select to ADDA–ADDC (via latch).

    2. Pulse START (min 100ns high).

    3. Wait for EOC = 1 (polling or interrupt).

    4. Set OE = 1, read data from D0–D7.

  • Timing: Conversion time ~100µs at 640kHz clock.

• DAC (DAC0800):

  • 8-bit current output DAC.

  • Interfacing: Connect data bus to D0–D7, CS and WR to I/O decode.

  • Operation: Write data to DAC → I_out = (V_ref × Data)/256.

  • Voltage Output: Use op-amp (e.g., LM741) as I–V converter with feedback resistor.

  • Update Rate: Limited by WR pulse and settling time.

END OF UNIT 4 NOTES
Prioritize: Timing diagrams, Addressing modes (8086/8051), 8255/8253/8257/8259/8251 control words, 8051 SFRs & interrupts, RISC vs CISC.