MICROPROCESSOR AND ITS APPLICATIONS (EC-501) - Unit 3 Short Notes

I. 8086 MICROPROCESSOR ARCHITECTURE & FUNDAMENTALS

Architecture & Organization

• Bus Interface Unit (BIU): Handles all bus operations (instruction fetch, I/O, memory read/write). Contains Instruction Pointer (IP), Segment Registers (CS, DS, SS, ES), and an Instruction Queue (6-byte).

• Execution Unit (EU): Executes instructions. Contains ALU, General Purpose Registers (AX, BX, CX, DX), Pointer & Index Registers (SP, BP, SI, DI), and Flag Register.

• Register Organization:

  • General Purpose: 16-bit (AX, BX, CX, DX). AX is accumulator; BX base; CX count; DX data.

  • Segment: CS (code), DS (data), SS (stack), ES (extra). Hold segment base addresses.

  • Pointer/Index: SP (stack pointer), BP (base pointer), SI (source index), DI (destination index).

  • Flag Register: 16-bit, with 9 active flags (CF, PF, AF, ZF, SF, TF, IF, DF, OF).

• Memory Organization: Segmentation

  • Physical 20-bit address space (1 MB) is logically divided into segments.

  • Physical Address Calculation:

$$\text{Physical Address} = (\text{Segment Register} \times 10\text{H}) + \text{Offset}$$

*   **Offset** is provided by IP, SP, SI, DI, BX, etc.

*   **Example**: If CS = 1234H and IP = 5678H, Physical Address = (1234H × 10H) + 5678H = 179B8H.

• Advantages of Segmentation:

  • Allows program/data to be placed anywhere in memory.

  • Enables memory > 64KB by using multiple segments.

  • Provides protection and modular programming.

• Even/Odd Memory Bank Organization:

  • 8086 has a 16-bit data bus (AD0-AD15). For even byte addresses, AD0=0 → full 16-bit access.

  • For odd byte addresses, AD0=1 → only upper byte (AD8-AD15) is enabled via BHE (Bus High Enable) signal.

  • Necessity: Allows byte/word access to any memory location without wasting memory.

Modes of Operation

• Minimum Mode (MN/MX=1): Single processor. 8086 generates all control signals (RD, WR, M/IO, ALE, DEN, DT/R).

• Maximum Mode (MN/MX=0): Multi-processor (with 8288 bus controller). 8086 outputs status signals (S0-S2); 8288 generates control signals.

• Comparison:

  | Feature | Minimum Mode | Maximum Mode | |----------------------|-------------------------------------------|-------------------------------------------| | Processors | Single | Multi-processor (with coprocessor) | | Control Signals | Generated by 8086 | Generated by 8288 Bus Controller | | Status Signals | Not used | S0, S1, S2 used by 8288 | | MN/MX Pin | Connected to +5V | Connected to GND |

• System Configuration (Minimum Mode):

  • Address Latch: 8282/8283 to latch address (AD0-AD15) during T1 (using ALE).

  • Bus Buffer/Driver: 8286/8287 for data bus (D0-D15) and control signals.

  • Clock Generator: 8284 for CLK, RESET, READY.

Timing Diagrams (Minimum Mode)

• Memory Read Cycle:

  • T1: Address (A0-A19, BHE) put on bus, ALE goes HIGH to latch address. M/IO = HIGH (memory).

  • T2: Address/data bus floated. RD goes LOW. DT/R = HIGH (read).

  • T3: Data from memory appears on bus. DEN goes LOW to enable bus receiver.

  • T4: RD and DEN go HIGH. Data read by EU.

  • Wait States (Tw): Inserted between T3 and T4 if READY=0.

• Memory Write Cycle:

  • T1: Address + ALE + M/IO=HIGH.

  • T2: Address floated. WR goes LOW. DT/R = LOW (write).

  • T3: Data from EU on bus. DEN goes LOW.

  • T4: WR and DEN go HIGH.

• Timing for Instructions (e.g., LXI H, MVI A):

  • LXI H, data16: 4 clock cycles (T1-T4). Opcode fetch + immediate data read.

  • MVI A, data8: 4 clock cycles (T1-T4). Opcode fetch + immediate data read.

  [!TIP] In timing diagrams, always note the state of M/IO, RD/WR, ALE, DEN, DT/R, and BHE.

II. 8086 INSTRUCTION SET & PROGRAMMING

Instruction Set Overview

• Classification:

  1. Data Transfer: MOV, PUSH, POP, XCHG, IN, OUT, LEA, LDS, LES.

  2. Arithmetic: ADD, ADC, SUB, SBB, INC, DEC, MUL, IMUL, DIV, IDIV, AAA, DAA.

  3. Logical: AND, OR, XOR, NOT, TEST, SHL/SAL, SHR, SAR, ROL, ROR, RCL, RCR.

  4. Branch: JMP, JC/JNC, JZ/JNZ, JS/JNS, JO/JNO, JP/JNP, LOOP, CALL, RET.

  5. Loop: LOOP, LOOPE/LOOPNE.

  6. String: MOVSB, MOVSW, CMPSB, SCASB, LODSB, STOSB (with REP prefix).

  7. Flag Manipulation: STC, CLC, STD, CLD, STI, CLI.

  8. Misc.: NOP, HLT, LOCK, ESC, WAIT.

• Key Instructions:

  • CMP: Subtract operands (dest - src) but don’t store result; only set flags (ZF, SF, CF, OF, AF, PF).

  • PUSHF: Push FLAGS register onto stack (SP = SP - 2, then write FLAGS).

  • SAR (Shift Arithmetic Right): Shift right preserving sign (MSB unchanged). Divides signed number by 2^n.

  • RCL (Rotate Through Carry Left): Rotate left through carry flag. CF gets last bit rotated out.

  • ADD: dest = dest + src; affects all arithmetic flags.

Addressing Modes

• Definition: Specifies how to calculate the Effective Address (Offset) of an operand.

• Types with Examples:

  | Mode | Syntax | Example | Offset Calculation | |------------------------|--------------------------------|----------------------|-------------------------------------| | Immediate | Operand is part of instruction | MOV AX, 1234H | No calculation (data is immediate) | | Register | Operand in register | MOV AX, BX | Offset = BX (if BX is used) | | Direct | Address given explicitly | MOV AX, [1234H] | Offset = 1234H | | Register Indirect | Offset in register (BX/BP/SI/DI)| MOV AX, [BX] | Offset = BX | | Based | Base (BX/BP) + Displacement | MOV AX, [BX+10H] | Offset = BX + 10H | | Indexed | Index (SI/DI) + Displacement | MOV AX, [SI+10H] | Offset = SI + 10H | | Based Indexed | Base + Index | MOV AX, [BX+SI] | Offset = BX + SI | | Relative Based Indexed | Base + Index + Displacement | MOV AX, [BX+SI+10H] | Offset = BX + SI + 10H | | Implied | Operand implied (e.g., STC) | STC | No operand |

• Displacement: 8-bit or 16-bit constant added to base/index.

• Base: BX (data segment) or BP (stack segment).

• Index: SI or DI.

Assembly Language Programming

• Program Structure:

  
  ASSUME CS:CODE, DS:DATA  ; Tell assembler segment registers
  
  DATA SEGMENT
  
      ; Data definitions (DB, DW, DD)
  
  DATA ENDS
  
  CODE SEGMENT
  
      START: MOV AX, DATA
  
             MOV DS, AX
  
             ; Instructions
  
             MOV AH, 4CH
  
             INT 21H        ; DOS terminate
  
  CODE ENDS
  
  END START
  
  

• Example Programs:

  1. Add two 16-bit numbers (in memory):

     
     MOV AX, [NUM1]   ; AX = NUM1
     
     ADD AX, [NUM2]   ; AX = AX + NUM2
     
     MOV [RESULT], AX ; Store result
     
     

  2. Find largest in array (10 numbers):

     
     LEA SI, ARRAY    ; SI points to array
     
     MOV CX, 10       ; Count
     
     MOV AL, [SI]     ; Assume first is max
     
     BACK: INC SI
     
           CMP AL, [SI]
     
           JAE SKIP    ; If AL >= [SI], skip
     
           MOV AL, [SI]; New max
     
     SKIP: LOOP BACK
     
     MOV MAX, AL
     
     

  3. Count frequency of byte BC in array (10 bytes):

     
     LEA SI, ARRAY    ; SI = offset of array
     
     MOV CX, 10       ; Count
     
     MOV AL, 'BC'     ; Data to search
     
     XOR BL, BL       ; BL = count = 0
     
     SEARCH: CMP [SI], AL
     
             JNE NEXT
     
             INC BL
     
     NEXT: INC SI
     
           LOOP SEARCH
     
     MOV FREQ, BL
     
     

  4. Sort ascending (Bubble sort):

     
     MOV CX, N-1      ; Outer loop count
     
     

  OUTER: LEA SI, ARRAY

     MOV DX, CX
  

  INNER: MOV AL, [SI]

     CMP AL, [SI+1]
  
     JBE SKIP_SWAP
  
     XCHG [SI], [SI+1] ; Swap
  

  SKIP_SWAP: INC SI

         DEC DX
  
         JNZ INNER
  
         LOOP OUTER
  
  ```
  

• Stack Operations:

  • PUSH: SP = SP - 2; Write register/memory at SS:SP.

  • POP: Read from SS:SP; SP = SP + 2.

  • Stack Segment: SS holds segment base. Top of stack = SS:SP (lowest address). Bottom is fixed (set by programmer).

  • Example: SS=2408H, SP=000AH. Top = 2408H:000AH. After PUSH AX (AX=1234H):

    • SP = 0008H

    • Memory: 2408H:0008H = 34H, 2408H:0009H = 12H.

    • After POP BX: BX=1234H, SP=000AH.

III. MEMORY & I/O INTERFACING

Memory Interfacing Concepts

• Address Decoding:

  • Absolute Decoding: All address lines decoded → unique address for each chip. No address overlap. Costly.

  • Partial Decoding: Only some address lines decoded → multiple addresses for same chip (memory fold). Saves hardware, but address space not fully utilized.

• Memory Map Design: Assign specific address ranges to each memory chip (RAM/ROM). Ensure no overlap.

• Interfacing Memory Chips:

  • Connect lower address lines (A0-A12 for 4K chip) to chip address pins.

  • Use higher address lines (A13-A19) with logic gates (NAND, AND) to generate Chip Select (CS).

  • Connect RD/WR (or M/IO) to chip’s OE/WE.

  • Connect data bus (D0-D15) directly.

• Example: Interface 32KB RAM & 2x 4Kx8 EPROM:

  • 32KB RAM = 32K × 8 = 2^15 locations → needs 15 address lines (A0-A14). CS from A15.

  • EPROM 1: 4K×8 → A0-A11. CS from A12, A13 (decoded to 000H-0FFFH).

  • EPROM 2: 4K×8 → A0-A11. CS from A12, A13 (decoded to 1000H-1FFFH).

  • Memory Map:

    • 00000H-00FFFH: EPROM 1

    • 01000H-01FFFH: EPROM 2

    • 02000H-09FFFH: RAM (32KB)

I/O Interfacing Concepts

• I/O-Mapped I/O:

  • Separate control signal M/IO = 0 for I/O.

  • Uses IN/OUT instructions (8-bit or 16-bit port address).

  • Full 16-bit address space for memory, 64KB for I/O.

• Memory-Mapped I/O:

  • I/O devices treated as memory locations.

  • Uses MOV instructions (same as memory access).

  • No separate M/IO; uses RD/WR.

  • Entire address space shared between memory and I/O.

• Comparison:

  | Feature | I/O-Mapped I/O | Memory-Mapped I/O | |----------------------|----------------------------------|---------------------------------| | Control Signal | M/IO = 0 | M/IO = 1 (or not used) | | Instructions | IN, OUT | MOV (any) | | Address Space | 64KB (16-bit port address) | Part of memory space | | Data Transfer | 8-bit/16-bit | 8-bit/16-bit (word aligned) | | Advantage | Dedicated I/O space | Full instruction set available |

Programmable Peripheral Interface (8255)

• Block Diagram: Three 8-bit ports (A, B, C). Control register. Data bus buffer. Read/Write control logic.

• Pin Diagram: PA0-PA7, PB0-PB7, PC0-PC7, RD, WR, CS, A0, A1, RESET.

• Modes of Operation:

  1. BSR (Bit Set/Reset) Mode:

     • Set/reset individual bits of Port C.

     • Control word format: D7=0 (BSR mode), D6-D3=Don’t care, D2-D0=Bit select (PC0-PC7).

     • Application: Generate square wave on PC pin, control individual pins (e.g., motor on/off).

     • Example: To set PC3: Control word = 00001000B (08H).

  2. I/O Modes:

     • Mode 0 (Basic I/O): Simple input/output, no handshaking. Ports A, B, C (upper/lower) can be input/output.

     • Mode 1 (Strobed I/O): Handshaking signals (STB, IBF, OBF, ACK). Used for interrupt-driven I/O. Port A/B can be Mode 1; Port C provides handshaking lines.

     • Mode 2 (Bidirectional Bus): Only Port A. Bidirectional data transfer with handshaking (INTR, IBF, OBF, STB, ACK). Used for data transfer with external devices (e.g., floppy).

• Control Word Format:

  • I/O Mode: D7=1. D6,D5: Port A mode. D4: Port A direction (1=IN). D3: Port C upper direction. D2: Port B mode. D1: Port B direction. D0: Port C lower direction.

  • BSR Mode: D7=0. D6-D3: X. D2-D0: Bit select.

• Interfacing Examples:

  • 8 ON/OFF Switches: Connect switches to Port A (Mode 0, input). Read switches via IN instruction.

  • 10-Key Matrix Keyboard: Use Port A (rows) as output, Port B (columns) as input (Mode 0). Scan rows sequentially, read columns.

  • 7-Segment Display: Connect display to Port A/B (Mode 0, output). Send BCD code to display digit.

• Interfacing 8255 to 8086 Low Byte (D0-D7):

  • Connect D0-D7 of 8255 to D0-D7 of 8086.

  • Connect A0, A1 of 8255 to A0, A1 of 8086.

  • Use A2-A19 for address decoding to generate CS.

  • Connect RD, WR to 8255’s RD, WR.

  • Example addresses: Port A=00H, Port B=02H, Port C=04H, Control=06H (as in Nov 2022).

IV. PROGRAMMABLE INTERRUPT CONTROLLER (8259A)

• Block Diagram: Interrupt Request Register (IRR), In-service Register (ISR), Priority Resolver, Interrupt Mask Register (IMR), Control Logic, Data Bus Buffer, Read/Write Logic.

• Functional Components:

  • IRR: Holds pending interrupt requests (IR0-IR7).

  • ISR: Holds interrupts being serviced (bits set during INTA, cleared on EOI).

  • Priority Resolver: Determines highest priority pending interrupt (IR0 highest, IR7 lowest in fully nested).

  • IMR: Masks interrupts (1=mask, 0=enable).

• Modes of Operation:

  • Fully Nested: Default. IR0 highest priority. Lower priority interrupts can be nested if not masked.

  • Automatic Rotation: After servicing an interrupt, its priority becomes lowest. Ensures fair share.

  • Specific Rotation: Rotate to specific IRQ (set by OCW2).

  • EOI (End of Interrupt): Sent by CPU (via OCW2) to clear ISR bit after ISR completes.

• Cascading: One master 8259 (IR0-IR7 connected to slave 8259s) + up to 8 slaves. Master handles interrupt from slaves. Requires cascade lines (CAS0-CAS2).

• Command Words:

  • ICW1: Start initialization. D4=1 for ICW4 needed. Edge/level trigger, single/cascade.

  • ICW2: Interrupt vector base address (bits 0-2 for IR0-IR7).

  • ICW3: For master/slave identification (cascading). Master: which IR connects to slave? Slave: its ID (0-7).

  • ICW4: 8086/8088 mode (D0=1), auto/normal EOI, buffer mode, etc.

  • OCW1: Interrupt Mask (IMR).

  • OCW2: EOI, rotate commands.

  • OCW3: Read IRR/ISR, poll command, special mask mode.

• 8086 Interrupt Structure:

  • Hardware: NMI (non-maskable, vector 2), INTR (maskable, via 8259).

  • Software: INT n (software interrupt, vector n), INTO (interrupt on overflow, vector 4).

  • Interrupt Vector Table: Located at 0000:0000. Each vector is 4 bytes (CS:IP). Vector address = n × 4.

V. PROGRAMMABLE INTERVAL TIMER (8253/8254)

• Block Diagram: Three independent 16-bit counters (Counter 0,1,2). Control Word Register. Read/Write Logic. Data Bus Buffer.

• Functional Blocks:

  • Counter: 16-bit down counter. OUT pin changes state when counter reaches 0.

  • Control Word Register: Written to select counter, mode, read/write format, BCD/binary.

• Modes of Operation:

  | Mode | Name | Description | Application | |----------|-------------------|------------------------------------------------------|-------------------------------| | 0 | Interrupt on Terminal Count | OUT goes HIGH after count reaches 0. | Event detection | | 1 | Hardware Retriggerable One-Shot | OUT goes LOW on gate, HIGH after count. | Pulse generation | | 2 | Rate Generator | Periodic square wave (OUT HIGH for half cycle). | Clock generation | | 3 | Square Wave | Similar to Mode 2, but symmetric (50% duty). | Baud rate generation | | 4 | Software Triggered Strobe | OUT HIGH for one CLK after trigger. | Strobe signal | | 5 | Hardware Triggered Strobe | OUT HIGH for one CLK after gate trigger. | Strobe on external event |

• Control Word Format:

  • D7-D6: Select counter (00=C0, 01=C1, 10=C2, 11=Read-back).

  • D5-D4: Read/Write (00=latched, 01=LSB only, 10=MSB only, 11=LSB then MSB).

  • D3-D1: Mode (000-101).

  • D0: BCD (0=binary, 1=BCD).

• Interfacing 8253/8254 to 8086:

  • Connect D0-D7 to 8086 data bus.

  • Connect A0, A1 to select counter/control (e.g., C0=00H, C1=02H, C2=04H, Control=06H).

  • Use A2-A19 for address decoding to generate CS.

  • Connect RD, WR to 8253’s RD, WR.

  • Connect CLK (external clock), GATE, OUT as needed.

• Square Wave Generation Flowchart:

  1. Write control word to select counter, Mode 3, LSB/MSB.

  2. Write count (LSB then MSB) to selected counter.

  3. Counter starts counting on GATE HIGH.

  4. OUT pin generates square wave (frequency = CLK / count).

VI. DMA CONTROLLER (8257)

• Need for DMA: For high-speed data transfer between I/O and memory without CPU intervention. Increases speed, frees CPU.

• DMA Transfer Cycle:

  1. HOLD: Peripheral requests DMA (DREQ to 8257).

  2. HLDA: 8257 requests bus from CPU (via HOLD). CPU relinquishes bus (floats lines) and asserts HLDA.

  3. Active Transfer: 8257 takes control. It provides address (via address bus) and control signals (MEMR, MEMW, IOR, IOW). Transfers one byte/word.

  4. Terminal Count (TC): When word count reaches 0, TC goes HIGH. Can generate interrupt.

  5. Return Bus: 8257 releases bus, HLDA goes LOW, CPU regains control.

• Register Organization:

  • Channel Registers (per channel 0-3):

    • Current Address Register: Holds 16-bit memory address. Auto-increments/decrements after transfer.

    • Current Word Count Register: 16-bit. Counts down to 0. TC generated when 0.

  • Command/Status Registers:

    • Mode Set Register: Enable/disable channels, fixed/auto-initialize, read/write priority, DREQ/DACK polarity.

    • Status Register: Read TC status (which channel reached TC), update pending.

    • Request Register: Software DREQ (for testing).

• Programming 8257:

  • Initialize Mode Set (auto-initialize, priority).

  • For each channel: Load Current Address, Current Word Count.

  • Enable channel via Mode Set.

  • On DREQ, DMA occurs automatically.

• Example: Transfer 2KB from memory 75000H to channel 1. I/O ports at 70H. Transfer 4 MSBs via port 80H.

  • Channel 1 Current Address = 75000H.

  • Current Word Count = 2KB / 1 (if 8-bit) or /2 (if 16-bit) = 512 or 1024.

  • Mode Set: Enable Ch1, auto-initialize, fixed priority.

  • 4 MSBs of address (75H) sent to output port 80H (via separate port, as in Nov 2022).

VII. SERIAL COMMUNICATION (8251 USART)

• Block Diagram: Transmitter (parallel-to-serial), Receiver (serial-to-parallel), Baud Rate Generator, Control Logic, Data Bus Buffer, Status/Control registers.

• Functional Units:

  • Transmitter: Holds data in buffer, converts to serial (start bit, data, parity, stop bits), shifts out on TXD.

  • Receiver: Samples RXD, assembles bits, stores in buffer, checks parity/stop.

  • Baud Rate Generator: Generates clock from external clock (e.g., 1.8432 MHz) for desired baud rate.

  • Control Logic: Interfaced to CPU via data bus, RD, WR, CS.

• Control Word:

  • Mode Instruction: Sets sync/async, character length (5-8 bits), parity (even/odd/1/0), stop bits (1, 1.5, 2). Written to control port.

  • Command Instruction: Enables TX/RX, sets DTR, RTS, break, etc. Written to same control port.

• Operation:

  • Asynchronous: Start bit (0), 5-8 data bits, optional parity, 1-2 stop bits (1). No sync clock.

  • Synchronous: Sync characters (1 or 2) sent first, then continuous data. Clock provided externally or internally.

• Interfacing 8251 with 8086:

  • Connect D0-D7 to 8086 data bus.

  • Use address lines (A0, A1) to select data port (read/write) and control port (write only).

  • Connect RD, WR, CS.

  • Connect TXD, RXD, modem control signals (DTR, RTS, CTS, DSR) as needed.

  • Connect clock to baud rate generator.

• USART vs UART:

  • UART: Only asynchronous communication.

  • USART: Supports both asynchronous and synchronous.

VIII. A/D & D/A CONVERSION

ADC (0808/0809)

• Block Diagram: 8-bit successive approximation ADC. 8 analog inputs (IN0-IN7). Reference voltage (Vref+, Vref-). Control logic (START, ALE, OE, CLK, EOC).

• Pins:

  • IN0-IN7: Analog inputs.

  • Vref+, Vref-: Reference (typically 0V and +5V).

  • START: High-to-low pulse starts conversion.

  • ALE: Latches address (selects IN0-IN7) when HIGH.

  • CLK: External clock (max 640 kHz).

  • EOC: Goes LOW during conversion, HIGH when done.

  • OE: Output enable (active HIGH). When HIGH, digital output appears on D0-D7.

• Conversion Time: ~100 µs (at 640 kHz clock).

• Interfacing with 8086:

  • Connect D0-D7 to 8086 data bus.

  • Use address decoding to generate CS (select ADC).

  • Connect A0-A2 to select analog channel (IN0-IN7).

  • Connect START, ALE, OE to output ports (or same address with write/read).

  • Connect EOC to input port (or interrupt input).

  • Procedure:

    1. Output channel number to address lines (via latch) and pulse ALE.

    2. Pulse START (via output port).

    3. Wait for EOC=HIGH (polling or interrupt).

    4. Set OE=HIGH (via output port).

    5. Read data from D0-D7.

    6. Set OE=LOW.

DAC Interfacing

• Basic DAC (e.g., 0800): 8-bit current output DAC. Needs external op-amp for voltage output.

• Interfacing:

  • Connect D0-D7 to 8086 data bus.

  • Address decode to generate CS.

  • Connect WR to DAC’s write input.

  • Procedure: Output digital value to DAC’s data port (using OUT instruction). Analog voltage appears at output.

IX. ADVANCED PROCESSORS (CISC vs RISC & Intel Family)

CISC vs RISC

• Examples: CISC – Intel x86, 8051. RISC – ARM, MIPS, SPARC.

Intel 80286

• Salient Features:

  • 16-bit data and address bus (24-bit addressing → 16 MB).

  • Protected Mode: Memory protection (privilege levels), multitasking, virtual memory support.

  • Memory management unit (MMU) for segmentation (like 8086 but with protection).

  • Upward compatible with 8086 (real mode).

  • Clock speed: 6-12.5 MHz.

Intel 80386

• Salient Features:

  • First 32-bit x86 processor.

  • 32-bit registers (EAX, EBX, etc.), 32-bit address bus (4 GB).

  • Paging: 4KB pages, two-level page tables. Enables virtual memory.

  • Protected Mode: Enhanced with paging, 32-bit segmentation.

  • Multitasking: Hardware support for task switching (TSS).

  • Virtual 8086 Mode: Run multiple 8086 programs in protected mode.

  • Clock speed: 16-33 MHz.

Pentium Processor

• Salient Features:

  • Superscalar Architecture: Two integer pipelines (U-pipe and V-pipe) → can execute 2 instructions per clock.

  • Separate Caches: 8KB instruction cache, 8KB data cache (Harvard architecture).

  • Burst Cycle Operation: Fast burst reads/writes (4 or 8 cycles) for cache fills.

  • Branch Prediction: Static prediction (always taken/not taken) to reduce stalls.

  • Floating-Point Unit (FPU): Integrated (387-compatible).

  • Pipelined, 5-stage (U-pipe), 6-stage (V-pipe).

  • Clock speeds: 60-200 MHz.

X. 8051 MICROCONTROLLER

Architecture & Block Diagram

• Internal Blocks:

  • CPU: 8-bit ALU, accumulator (ACC), B register, PSW, PC, SP.

  • Memory: 4KB on-chip ROM (program), 128B on-chip RAM (data), 128B SFR space.

  • I/O Ports: Four 8-bit ports (P0-P3), multiplexed with alternate functions.

  • Timers/Counters: Two 16-bit timers (T0, T1).

  • Serial Unit: Full-duplex UART (mode 0-3).

  • Interrupt System: 5 sources (2 external, 2 timers, 1 serial).

  • Clock Circuit: Internal oscillator (XTAL1/XTAL2).

• Pin Diagram (40-pin DIP):

  • P0.0-P0.7: Multiplexed with address/data bus (low byte). Open-drain.

  • P1.0-P1.7: Pure I/O (quasi-bidirectional).

  • P2.0-P2.7: Multiplexed with high address byte (A8-A15).

  • P3.0-P3.7: Alternate functions: RXD, TXD, INT0, INT1, T0, T1, WR, RD.

  • ALE: Address Latch Enable. Demultiplexes P0.

  • PSEN: Program Store Enable. Read from external ROM.

  • EA: External Access. EA=1 → on-chip ROM first; EA=0 → external ROM only.

  • RST: Reset input (active HIGH). Sets PC=0000H.

  • XTAL1/XTAL2: Crystal oscillator connections.

  • VCC, GND.

Memory Organization & Access

• Program Memory:

  • On-chip: 0000H-0FFFH (4KB). Accessed when EA=1 and PC<0FFFH.

  • Off-chip: If EA=0 or PC≥0FFFH, external ROM accessed via PSEN (active LOW) and P0/P2 (address).

• Data Memory:

  • On-chip RAM: 00H-7FH (128B). Direct/indirect addressing.

  • SFR: 80H-FFH (128B). Direct addressing only.

  • Off-chip RAM: Up to 64KB. Accessed with MOVX (external data move). P0/P2 provide address; RD/WR control.

Register Organization & SFRs

• Accumulator (ACC/A): 8-bit. Used for arithmetic/logic.

• B Register: 8-bit. Used for MUL/DIV.

• Program Status Word (PSW):

  • CY (carry), AC (aux carry), F0 (flag), RS1, RS0 (register bank select), OV (overflow), – (unused), P (parity).

• Stack Pointer (SP): 8-bit. Points to on-chip RAM (default 07H). PUSH/POP use SP.

• Data Pointer (DPTR): 16-bit. Used for external memory addressing (MOVX @DPTR).

• Port Registers: P0, P1, P2, P3 (address 80H, 90H, A0H, B0H).

• Timer Control: TCON (88H), TMOD (89H).

• Serial Control: SCON (98H), SBUF (99H).

• Interrupt Enable: IE (A8H), IP (B8H).

• Power Control: PCON (87H) – idle mode, slow mode (SMOD for serial).

Addressing Modes

Instruction Set Highlights

• Data Transfer: MOV (all modes), XCHG (exchange A with reg/mem), XCHD (exchange nibble), PUSH/POP (direct/indirect), MOVC (code memory), MOVX (external).

• Arithmetic: ADD, ADDC, SUBB, DA (decimal adjust), INC, DEC, MUL, DIV.

• Logical: ANL, ORL, XRL, CLR, CPL, RL/RR (rotate), RLC/RRC (rotate through carry), SWAP (swap nibbles).

• Rotate & Swap:

  • RL A: Rotate left (MSB → LSB, MSB → CY).

  • RLC A: Rotate left through carry (MSB → CY, CY → LSB).

  • SWAP A: Swap upper and lower nibbles (A3-A0 ↔ A7-A4).

Interrupt Structure

• Sources:

  • External: INT0 (P3.2, vector 0003H), INT1 (P3.3, vector 0013H).

  • Timer: TF0 (T0 overflow, vector 000BH), TF1 (T1 overflow, vector 001BH).

  • Serial: RI/TI (serial receive/transmit, vector 0023H).

• Interrupt Priority: Fixed order: INT0 → TF0 → INT1 → TF1 → RI/TI.

• Interrupt Enable/Disable:

  • IE Register (A8H):

    • EA (global enable), ES (serial), ET1 (timer1), EX1 (int1), ET0 (timer0), EX0 (int0).

  • IP Register (B8H): Set bits for high priority (default low).

• Polling Sequence: If multiple interrupts pending, CPU services in fixed order (INT0 highest).

• Hardware vs Software Interrupts:

  • Hardware: External pins (INT0, INT1), internal events (TF0, TF1, RI/TI).

  • Software: None in 8051 (no INT instruction). But external interrupts can be triggered by software (by toggling INT pin).

I/O Ports

• Port 0: Multiplexed AD0-AD7. Open-drain. Needs external pull-up. Used as address/data bus for external memory.

• Port 2: Multiplexed A8-A15. Used as high address byte for external memory. Quasi-bidirectional.

• Port 3: Alternate functions:

  • P3.0 = RXD (serial input)

  • P3.1 = TXD (serial output)

  • P3.2 = INT0 (external interrupt 0)

  • P3.3 = INT1 (external interrupt 1)

  • P3.4 = T0 (timer 0 external input)

  • P3.5 = T1 (timer 1 external input)

  • P3.6 = WR (external memory write strobe)

  • P3.7 = RD (external memory read strobe)

Serial Communication

• Modes:

  • Mode 0: Synchronous, 8-bit shift register. Clock on TXD (fosc/12). Used for shift register I/O.

  • Mode 1: 8-bit UART, variable baud rate (from timer 1 or 2). 1 start, 8 data, 1 stop.

  • Mode 2: 9-bit UART, fixed baud rate (fosc/32 or /64). 1 start, 9 data (TB8/RB8), 1 stop. Multiprocessor communication.

  • Mode 3: 9-bit UART, variable baud rate (from timer 1 or 2).

• SFRs for Serial:

  • SCON (98H):

    • SM0, SM1: Mode select.

    • SM2: Multiprocessor enable (Mode 2/3).

    • REN: Receive enable.

    • TB8: 9th bit for transmit (Mode 2/3).

    • RB8: 9th bit received (Mode 2/3).

    • TI: Transmit interrupt flag (set when data moved to shift register).

    • RI: Receive interrupt flag (set when data in SBUF).

  • SBUF (99H): Serial data buffer (write for transmit, read for receive).

  • PCON (87H): SMOD (double baud rate in Mode 1/3 when set).

Embedded Systems Context

• Embedded System: Special-purpose computer system designed for specific tasks, often with real-time constraints. Embedded within larger device.

• Classification:

  • Based on Performance: Small-scale (4-bit/8-bit), Medium-scale (16-bit), Large-scale (32-bit/64-bit).

  • Based on Complexity: Simple (no OS), Complex (with RTOS).

  • Based on Triggering: Event-driven, Real-time (hard/soft).

• Role of 8051: Used in automotive, industrial control, consumer electronics, robotics due to low cost, low power, on-chip peripherals.

END OF UNIT 3 SHORT NOTES
Based on RGPV EC-501 past papers (May 2023 – Jun 2025).