MICROPROCESSOR AND ITS APPLICATIONS (EC-501) - Unit 2 Short Notes

UNIT 2: 8086/88 MICROPROCESSOR & APPLICATIONS

I. 8086/88 Microprocessor Architecture & Fundamentals

Functional Block Diagram

The 8086 is a 16-bit HMOS microprocessor with a 20-bit address bus and 16-bit data bus. It contains two independent units:

1. Bus Interface Unit (BIU): Handles all bus operations (address generation, instruction fetching, reading/writing from/to memory or I/O). Contains Instruction Pointer (IP), Segment Registers (CS, DS, SS, ES), and an Instruction Queue (6 bytes).

2. Execution Unit (EU): Executes instructions. Contains General Purpose Registers (AX, BX, CX, DX), Pointer/Index Registers (SP, BP, SI, DI), ALU, and Flag Register (PSW).

Key Interaction: BIU fetches instructions into the queue while EU executes them. This pipelining allows concurrent fetch and execute, improving speed.

Register Organization

Flag Register (PSW) Details

Memory Organization & Addressing

• Segmentation: 1MB memory ($$\displaystyle 2^{20} $$) is divided into 16 segments of 64KB each. A logical address is Segment:Offset.

• Physical Address Calculation:

$$Physical\ Address = (Segment\ Register \times 16) + Offset$$

Example: `CS:IP = 1234H:5678H` → Phys Addr = $$\displaystyle 12340H + 5678H = 179B8H $$.

• Advantages of Segmentation:

  • Allows program/data to be >64KB.

  • Provides memory protection & organization.

  • Facilitates relocation.

• Even/Odd Bank Organization: 8086 has a split data bus. Even-addressed bytes go to D15-D8 (high bank), Odd-addressed bytes to D7-D0 (low bank). A word at an even address (e.g., 1000H) is accessed in one bus cycle. A word at an odd address (e.g., 1001H) requires two bus cycles (misaligned access).

Address Decoding

• Absolute Decoding: All address lines are decoded to generate a unique CS for each memory chip. Simple but wasteful of address space.

• Partial Decoding: Only some high-order address lines are decoded. Multiple memory locations can share the same chip select range (e.g., 0000H-3FFFH and 4000H-7FFFH both activate same chip). Efficient but creates address mirroring.

Operating Modes

II. 8086/88 Timing Diagrams & Machine Cycles

Read Machine Cycle (Memory Read) - Minimum Mode

1. T1: ALE goes HIGH. Address (A19-A0, BHE) is put on bus and latched by external latch (using ALE).

2. T2: ALE goes LOW. Control signals RD & M/IO go LOW (active). Data bus is turned around (high-impedance) for read. DT/R is LOW (receive mode).

3. T3: Memory chip decodes address, places data on bus. READY must be HIGH. If READY is LOW, Twait states are inserted.

4. T4: RD goes HIGH (inactive). Data is read by 8086. DEN goes LOW to enable data bus buffer.

Write Machine Cycle (Memory Write) - Minimum Mode

Similar to read, but:

• M/IO = LOW (Memory), WR = LOW (active) in T2.

• DT/R = HIGH (transmit mode) in T2.

• Data must be stable on bus before WR goes active (setup time).

I/O Read/Write Cycles

Identical to memory cycles, but M/IO = HIGH for I/O. RD/WR pulses are same.

Interrupt Acknowledge Cycle

After INTR is recognized at end of an instruction, 8086 sends two INTA pulses. During 2nd INTA, external device places interrupt type (0-255) on data bus. 8086 stores it, fetches CS:IP from vector table (type × 4).

Timing for LXI H, data & MVI A, data

• LXI H, 16-bit data: 3 machine cycles (Opcode fetch + 2 memory reads for 16-bit immediate data).

• MVI A, 8-bit data: 2 machine cycles (Opcode fetch + 1 memory read for 8-bit immediate data).

III. 8086/88 Instruction Set & Programming

Classification (Key Types)

• Data Transfer: MOV, PUSH, POP, XCHG, XLAT, IN, OUT.

• Arithmetic: ADD, SUB, INC, DEC, MUL, DIV, ADC, SBB, AAA, DAA.

• Logical: AND, OR, XOR, NOT, TEST, SHL/SAL, SHR, SAR, ROL, ROR, RCL, RCR.

• Branch/Transfer: JMP, CALL, RET, Jcc (JE, JNE, JG, etc.).

• Loop: LOOP, LOOPE, LOOPNE.

• String: MOVSB, CMPSB, SCASB, LODSB, STOSB (with REP prefix).

• Flag Manip: STC, CLC, STD, CLD, STI, CLI.

• Machine Control: NOP, HLT, WAIT, LOCK, ESC, INT, INTO.

Addressing Modes

Displacement: 8-bit or 16-bit constant added to base/index. Base: BX or BP. Index: SI or DI. Effective Address (Offset): The 16-bit offset computed from addressing mode, added to segment base.

Assembly Programming Examples

• Addition of two 16-bit numbers (in registers):

  
  MOV AX, 1234H    ; Load first number
  
  ADD AX, 5678H    ; Add second number
  
  ; Result in AX, flags updated
  
  

• Multi-byte addition from different segments:

  
  MOV AX, [DS:0500H]  ; Load from DS:0500H (low word)
  
  MOV BX, [ES:0600H]  ; Load from ES:0600H (high word)
  
  ADD AX, BX          ; Add low words, carry in CF
  
  MOV [ES:0700H], AX  ; Store result low word
  
  ADC BX, 0000H       ; Add carry to high word
  
  MOV [ES:0702H], BX  ; Store result high word
  
  

• Find largest number in array (10 bytes):

  
  LEA SI, ARRAY      ; SI points to array start
  
  MOV CL, 10         ; Counter
  
  MOV AL, [SI]       ; Assume first is max
  
  DEC CL
  
  NEXT: INC SI
  
  CMP AL, [SI]
  
  JGE SKIP           ; Jump if current max >= array element
  
  MOV AL, [SI]       ; Update max
  
  SKIP: LOOP NEXT
  
  ; Max in AL
  
  

• Count frequency of byte BC in 10-byte array:

  
  LEA SI, ARRAY      ; Source array at 01BC:2842
  
  MOV DI, SI         ; Copy pointer
  
  MOV CX, 10         ; 10 elements
  
  XOR AL, AL         ; Clear counter (result)
  
  MOV BL, 'BC'       ; Data to search (0BCh)
  
  SEARCH: CMP [SI], BL
  
  JNE NOT_FOUND
  
  INC AL             ; Increment count
  
  NOT_FOUND: INC SI
  
  LOOP SEARCH
  
  MOV [DI], AL       ; Store result at same location (as per Q)
  
  

IV. Memory & I/O Interfacing with 8086/88

Memory Interfacing

• Chip Select (CS) Generation: Use decoders (74LS138). Connect high-order address lines (A15-A12) to decoder inputs. Outputs provide active-low CS for memory chips.

• Generating Control Signals (Min Mode):

  • MEMR = RD • M/IO (active low read for memory)

  • MEMW = WR • M/IO (active low write for memory)

  • IOR = RD • M/IO (active low read for I/O)

  • IOW = WR • M/IO (active low write for I/O)

Example: Interface two 4K×8 EPROMs (Total 8KB)

• Each EPROM: 4K = $$\displaystyle 2^{12} $$ locations → needs 12 address lines (A0-A11).

• Address map: EPROM1: 00000H-0FFFH; EPROM2: 1000H-1FFFH.

• Connect A0-A11 to both EPROMs' address pins.

• Connect A12 to 74LS138 input (say, C). Connect A13-A15 to other inputs (tied to GND for partial decode).

• CS1 = Output0 of 138 (when A12=0), CS2 = Output1 (when A12=1).

• MEMR connected to OE (Output Enable) of both EPROMs.

I/O Interfacing

• I/O Mapped I/O: Separate IOR/IOW control signals. 16-bit I/O address space (64K ports). IN/OUT instructions used. Does not use data/address bus for I/O addresses.

• Memory Mapped I/O: I/O devices are assigned memory addresses. Uses same MEMR/MEMW signals. MOV instructions used. Consumes memory address space.

• Comparison:

  | Feature | I/O Mapped | Memory Mapped | | :--- | :--- | :--- | | Address Space | Separate (64K I/O) | Part of memory space | | Control Signals | IOR, IOW | MEMR, MEMW | | Instructions | IN, OUT | MOV (any) | | Address Bus Use | 16-bit I/O address on bus | Full 20-bit memory address | | Data Transfer | 8-bit (usually) | 8/16-bit |

V. Programmable Peripheral Interface (8255/8155)

Block Diagram & Functional Description

• Three 8-bit ports: Port A, Port B, Port C (PC upper/lower can be split).

• Control Register: Programs mode of ports & BSR.

• Data Bus Buffer: 8-bit bidirectional interface to CPU.

• Read/Write Control Logic: Decodes CS, RD, WR, A0, A1.

• Port A/B/C: Each has latches/output buffers & input buffers.

Modes of Operation

1. Mode 0 (Simple I/O): Basic input/output. No handshaking. Ports A, B, C (upper/lower) can be input or output.

2. Mode 1 (Strobed I/O): Handshaking for Port A or B. Uses PC pins for control signals (e.g., STB, IBF, OBF, ACK). One port (A or B) in Mode 1, other in Mode 0.

3. Mode 2 (Bidirectional Bus): Only for Port A. Uses PC pins for bidirectional data bus control (handshaking both ways). Port B can be Mode 0 or 1.

BSR (Bit Set/Reset) Mode

• Special mode for controlling individual bits of Port C.

• Activated when D7=0 in Control Word.

• Format: 1 1 1 1 1 1 1 0 (D7=0) followed by 0 1 0 0 0 0 0 1 where:

  • D6-D3: Don't care (0)

  • D2-D0: Select bit of Port C (000=PC0, 001=PC1, ..., 111=PC7)

  • D4: Set (1) or Reset (0) the selected bit.

• Example: Set PC3 → Control Word = 10001001B = 89H.

Control Word Format

• For I/O Mode (D7=1):

  • D6, D5: Port A mode (00=Mode0, 01=Mode1, 1X=Mode2)

  • D4: Port A direction (1=Input, 0=Output)

  • D3: Port C upper direction (1=Input, 0=Output)

  • D2: Port B mode (1=Mode1, 0=Mode0)

  • D1: Port B direction (1=Input, 0=Output)

  • D0: Port C lower direction (1=Input, 0=Output)

• For BSR Mode (D7=0): As described above.

Interfacing 8255 with 8086 (Low Byte)

• Connect D0-D7 of 8086 to D0-D7 of 8255.

• Connect A0, A1 of 8086 (address lines) to 8255's A0, A1.

• Generate CS using address decoding (e.g., CS = /IOR + /IOW + A9 for I/O address range).

• Since 8086 data bus is 16-bit, for low-byte access: Connect BHE to a logic HIGH (or use DEN with BHE to enable only low byte buffer).

VI. Programmable Interrupt Controller (8259A)

Block Diagram & Functional Blocks

1. Interrupt Request Register (IRR): Holds pending interrupt requests (IR0-IR7).

2. In-service Register (ISR): Holds interrupts being serviced.

3. Priority Resolver: Determines highest priority pending interrupt (IR0 highest, IR7 lowest in fixed nested mode).

4. Interrupt Mask Register (IMR): Masks interrupts (1=masked).

5. Control Logic: Generates INT output to CPU, handles INTA cycles.

6. Data Bus Buffer: For read/write of ICWs/OCWs.

Modes of Operation

• Fully Nested: Default. IR0 highest priority. Lower priority interrupts can be nested if not masked.

• Automatic Rotation: After servicing an interrupt, its priority is set to lowest, others rotate up. Provides fair service.

• Specific Rotation: OCW2 with R and SL bits sets a specific IR to lowest priority.

• Special Mask Mode: Allows higher priority interrupts while servicing a lower one (by setting IMR dynamically).

Interrupt Sequence & Programming

1. Initialization (ICWs):

   • ICW1: A0=0. Sets edge/level trigger, single/cascade mode, ICW4 needed.

   • ICW2: A0=1. Sets interrupt vector base address (e.g., 08H for IR0 → vector at 08H, 10H for IR1, etc.).

   • ICW3: A0=1. Cascading - tells which IR is connected to slave's INT (for master) or slave ID (for slave).

   • ICW4: A0=1. Sets 8086/8080 mode, auto/normal EOI, buffer mode.

2. Operation (OCWs):

   • OCW1: A0=1. Interrupt Mask (set bits to mask).

   • OCW2: A0=0. End of Interrupt (EOI), rotate commands.

   • OCW3: A0=1. Read IRR/ISR, special mask, poll command.

Cascading: One master 8259A connects to up to 8 slave 8259As. Master's IR2 (example) connected to slave's INT. Master's ICW3 bit2=1. Slave's ICW3 sets its slave ID (0-7).

VII. Programmable Interval Timer (8253/8254)

Block Diagram & Functional Description

• Three independent 16-bit Counters (Counter 0, 1, 2).

• Control Word Register: Written to select counter, mode, read/write format.

• Read/Write Logic: Interfaces with data bus, handles read/write of counter registers.

• Address Lines: A0, A1 select counter/control.

• CLK Inputs: Each counter has its own clock (up to 2.6 MHz for 8254).

• GATE Inputs: Start/stop counting (level or edge triggered depending on mode).

• OUT Outputs: Generate waveforms/interrupts.

Modes of Operation

Control Word Format

• D7-D6: Select Counter (00=C0, 01=C1, 10=C2, 11=Read-back - 8254 only).

• D5-D4: Read/Write mode (00=latch, 01=LSB only, 10=MSB only, 11=LSB then MSB).

• D3-D1: Select Mode (000 to 101).

• D0: BCD (0=Binary, 1=BCD).

Programming Example (Mode 3 - Square Wave):

MOV AL, 36H    ; Counter 0, Mode 3, LSB then MSB, binary

OUT 0EH, AL    ; Write to Control Word (port 0Eh)

MOV AX, 1000   ; Count = 1000

OUT 08H, AL    ; Write LSB to Counter 0 (port 08h)

MOV AL, AH

OUT 08H, AL    ; Write MSB

; OUT0 generates square wave of freq = CLK / 1000

VIII. DMA Controller (8257)

Need for DMA: Allows peripheral-to-memory or memory-to-peripheral data transfer without CPU intervention, freeing CPU for other tasks. Essential for high-speed data transfer (disk, video).

Register Organization

• Channel Registers (x4): Each channel has:

  • DMA Address Register: 16-bit starting memory address.

  • Word Count Register: 16-bit number of words to transfer.

• Temporary Address Register: Holds address during transfer (for memory-to-memory mode - 8257 only).

• Mode Set Register: Programs channel priority (fixed/rotating), auto-increment, DMA read/write, memory-to-memory mode.

• Status Register: Contains terminal count (TC) flags for each channel, error flags.

• Command Register: Software control (clear TC, enable/disable channels).

DMA Transfer Cycle (HOLD/HLDA)

1. HOLD Request: Peripheral asserts HRQ (HOLD Request) to 8257.

2. HLDA Grant: 8257 asserts HLDA (HOLD Acknowledge) to CPU after completing current bus cycle.

3. DMA Cycle: 8257 takes control of bus. It places memory address on address bus, activates MEMR/MEMW and IOR/IOW as needed, transfers data. Byte count decremented.

4. End of Transfer: When Word Count = 0, TC (Terminal Count) bit set for that channel. HRQ goes inactive, HLDA goes inactive, CPU regains bus.

Fixed vs. Rotating Priority:

• Fixed: Channel 0 highest, Channel 3 lowest (or vice versa via mode set).

• Rotating: After a channel completes transfer, its priority becomes lowest, others rotate up. Fair share.

IX. Serial Communication & USART (8251)

Synchronous vs. Asynchronous

8251 Block Diagram & Operation

• Transmitter: Parallel-to-serial converter, adds start/stop/parity bits (async) or sync chars. Output via TXD.

• Receiver: Serial-to-parallel converter, removes start/stop/parity, checks errors. Input via RXD.

• Baud Rate Generator: Generates clock from external TxC/RxC or internal (using external crystal).

• Control/Status Registers: Written/read by CPU to configure mode, send commands, check status.

Control Word Format

• Mode Instruction (written first):

  • D7-D6: Character length (5,6,7,8 bits).

  • D5: Parity enable/disable.

  • D4: Even/Odd parity.

  • D3-D2: Stop bits (async: 1, 1.5, 2; sync: 2 sync chars).

  • D1-D0: Synchronous mode (00=async, 01=1-char sync, 10=2-char sync, 11=external sync).

• Command Instruction (written after mode):

  • D7: E/D (Enable/Disable transmitter).

  • D6: RTS (Request To Send).

  • D5: DTR (Data Terminal Ready).

  • D4: RxEN (Receiver Enable).

  • D3: DTR (internal reset).

  • D2: SBRK (Send break).

  • D1: ER (Error Reset).

  • D0: IR (Internal Reset - software reset).

Status Word & Bits

Interfacing with 8086: Connect data bus, RD, WR, CS (decoded I/O address). Connect TXD/RXD to serial line. Connect TxC/RxC for external clock or use internal (crystal on RxC).

X. Analog Interfacing

ADC 0808/0809

• 8-bit, 8-channel multiplexed ADC.

• Key Pins:

  • IN0-IN7: Analog inputs.

  • ADDA, ADDB, ADDC: Address lines to select channel.

  • ALE: Latch address on rising edge.

  • START: Rising edge starts conversion.

  • EOC (End of Conversion): Goes LOW during conversion, HIGH when done.

  • OE (Output Enable): When HIGH, digital output appears on D0-D7.

  • CLK: Clock input (max 640kHz).

• Conversion Time: ~100µs at 640kHz.

• Interfacing:

  1. Output channel address to ADDA-C and pulse ALE.

  2. Pulse START (can be same as ALE).

  3. Poll EOC (wait for HIGH) or use interrupt.

  4. Set OE=1 to read data from D0-D7.

DAC 0800

• 8-bit, current-output DAC.

• Key Pins:

  • D0-D7: Digital input.

  • Iout: Current output (proportional to digital value).

  • Rfb: Feedback resistor (connect to op-amp for voltage output).

  • Vref: Reference voltage (sets full-scale).

• Interfacing:

  • Connect data bus to D0-D7.

  • Generate CS (I/O or memory decoded).

  • For voltage output: Connect Iout to inverting input of op-amp, Rfb from output to inverting input, Vref to non-inverting.

  • Write digital value to DAC port → analog voltage = (Digital Value / 256) × Vref.

Waveform Generation: Use software loop to write increasing/decreasing values to DAC for sawtooth/square waves. Use 8253 timer to trigger DAC updates for precise frequency.

XI. 8051 Microcontroller

Architecture & Organization

• CPU Core: 8-bit ALU, PSW, 16-bit PC.

• On-Chip Memory:

  • ROM/EPROM: 4KB (0000H-FFFFH) for program (if present). External ROM accessed via PSEN.

  • RAM: 128 bytes (00H-7FH) for data. Upper 128 bytes (80H-FFH) are SFRs.

• I/O Ports: Four 8-bit ports (P0-P3). Dual Functions:

  • P0: AD0-AD7 (multiplexed address/data for external memory), open-drain.

  • P1: Pure I/O.

  • **P2: A8-A15` for external memory.

  • P3: Alternate functions:

    | Pin | Alt Function | Purpose | | :--- | :--- | :--- | | P3.0 | RXD | Serial input | | P3.1 | TXD | Serial output | | P3.2 | INT0 | External interrupt 0 | | P3.3 | INT1 | External interrupt 1 | | P3.4 | T0 | Timer 0 external input | | P3.5 | T1 | Timer 1 external input | | P3.6 | WR | External memory write strobe | | P3.7 | RD | External memory read strobe |

• Other Pins:

  • ALE: Address Latch Enable. Latches low byte of address from P0.

  • PSEN: Program Store Enable. Read from external ROM.

  • RST: Reset input (active HIGH). Sets PC=0000H, clears SFRs (except SBUF, TH/TL in mode 2/3).

  • XTAL1, XTAL2: Crystal oscillator connections.

Special Function Registers (SFRs)

PSW Format:

Bit 7  6  5  4  3  2  1  0

      CY AC F0 RS1 RS0 OV - P

RS1-RS0: Select Register Bank (0-3)

Addressing Modes (8051)

Interrupt Structure

• Sources:

  • External: INT0 (P3.2, vector 0003H), INT1 (P3.3, vector 0013H).

  • Timer: TF0 (Timer0 overflow, vector 000BH), TF1 (Timer1 overflow, vector 001BH).

  • Serial: RI/TI (Serial receive/transmit, vector 0023H).

• Priority: Natural order: INT0 > TF0 > INT1 > TF1 > RI/TI. Can be changed via IP register.

• Enable: Global EA in IE must be 1. Individual enable bits (EX0, ET0, etc.).

• Sequence: CPU finishes current instruction, pushes PC, fetches vector from table (fixed addresses), jumps to ISR. ISR must end with RETI.

Timer/Counters (TMOD & TCON)

• TMOD Format:

  
  GATE C/T M1 M0 | GATE C/T M1 M0
  
  (T1)           | (T0)
  
  

  • GATE: 1=Timer runs only while INTx pin HIGH.

  • C/T: 0=Timer (internal clock), 1=Counter (external pulses on T0/T1).

  • M1 M0: Mode (00=13-bit timer, 01=16-bit, 10=8-bit auto-reload, 11=split mode).

• TCON Bits:

  • TF1, TF0: Timer overflow flags (set by hardware, cleared by software).

  • TR1, TR0: Timer run control bits (1=start).

XII. Advanced Processors (Comparative Study)

RISC vs. CISC

Evolution: 80286 → 80386 → 80486 → Pentium

• 80286:

  • 16-bit data/address (24-bit addr → 16MB).

  • Protected Mode: Memory protection, multitasking, privilege levels (0-3).

  • New instructions: PUSHA, POPA, BOUND, ARPL, CLTS.

  • Memory Management Unit (MMU): Descriptor tables (GDT, LDT).

• 80386:

  • 32-bit architecture (EAX, CR0-CR3, EFLAGS).

  • 32-bit address bus → 4GB physical memory.

  • Paging: 4KB pages, two-level page tables.

  • Virtual 8086 Mode: Run 8086 code in protected mode.

  • New registers: EAX, EBX, ..., EIP, EFLAGS, CS, DS, ..., segment descriptors 32-bit.

• 80486:

  • On-chip 8KB cache (unified).

  • Pipelined FPU (on-chip).

  • RISC-like micro-ops: Complex instructions decoded to simple RISC ops internally.

  • BIST (Built-In Self Test).

• Pentium:

  • Superscalar: Dual pipelines (U-pipe & V-pipe). Can execute 2 instructions per clock.

  • Separate 8KB Instruction & Data Caches (Harvard architecture).

  • Branch Prediction: 256-entry BTB (Branch Target Buffer).

  • Burst Cycle: Fast cache line fill (4-word burst).

  • U-pipe: Can handle any instruction. V-pipe: Limited to simple, pairable instructions (U-pipe & V-pipe can execute simultaneously if no dependencies).

Pentium Pipelining Example: ADD EAX, EBX (U-pipe) + MOV ECX, [EDX] (V-pipe) can execute in parallel if no resource conflict.

UNIT 2 EXAM TIPS

[!TIP] Timing Diagrams: Always label T-states, show ALE (T1), RD/WR (T2-T4), READY wait states, and data setup/hold times. For LXI/MVI, show opcode fetch + immediate data read cycles.

[!TIP] Addressing Modes: Distinguish Based ([BP+disp]) vs Indexed ([SI+disp]) vs Based Indexed ([BX+SI]). Remember [BP] defaults to SS, others to DS.

[!TIP] 8255 BSR vs I/O Mode: BSR controls individual bits of Port C only (no data transfer). I/O mode moves 8-bit bytes on Ports A/B/C.

[!TIP] 8253 Mode 3: For square wave, count must be even for 50% duty. If odd, high pulse = (N+1)/2, low = N/2 cycles.

[!TIP] 8051 Memory Access: On-chip ROM (0000H-FFFFH) accessed automatically when PSEN active. External ROM uses PSEN + ALE/P2. On-chip RAM (00H-7FH) accessed directly. External RAM uses RD/WR + P0/P2.

[!TIP] Stack Operations: PUSH decrements SP by 2, then stores. POP reads, then increments SP by 2. Stack grows downwards (to lower addresses).

[!TIP] Flag Changes: CMP is SUB without storing result → affects SF, ZF, AF, PF, CF, OF. TEST is AND without store → affects SF, ZF, PF.

[!TIP] Physical Address: Always calculate as (segment × 10H) + offset. Result is 20-bit. Example: DS:SI = 1234H:5678H → 12340H + 5678H = 179B8H.

[!TIP] 8259A Cascading: Master's ICW3 has a bit for each IR (if IR2 connects to slave, bit2=1). Slave's ICW3 sets its slave ID (0-7). Master receives interrupt type from slave.