MICROPROCESSOR AND ITS APPLICATIONS (EC-501) - Unit 1 Short Notes

UNIT 1: MICROPROCESSOR AND ITS APPLICATIONS

I. INTRODUCTION TO MICROPROCESSOR SYSTEMS

A. CISC vs RISC Architecture

[!TIP] Exam Focus: CISC emphasizes hardware complexity for software simplicity; RISC emphasizes hardware simplicity for software complexity. Modern processors (like Intel Core) use CISC ISA with RISC-like microarchitecture (micro-ops).

B. Evolution of Microprocessors

• 4-bit (1971): Intel 4004 (first commercial MPU), 740 kHz, 2,300 transistors.

• 8-bit (1974): Intel 8080, Motorola 6800. Introduced more registers, better I/O.

• 16-bit (1978): Intel 8086 (first x86), 16-bit data/address bus, segmentation, 29,000 transistors.

• 32-bit (1985): 80386 introduced 32-bit registers/address bus (4GB), paging, virtual 8086 mode.

• Pentium (1993): First superscalar x86 (dual pipelines), separate caches, branch prediction.

• 64-bit (2003): AMD Opteron (x86-64), Intel Itanium (IA-64, EPIC), extended registers to 64-bit.

C. Intel Microprocessor Family Overview

D. Embedded Systems

• Definition: A specialized computing system that performs dedicated functions within a larger mechanical/electrical system, often with real-time constraints.

• Characteristics: Dedicated function, resource constraints (cost, power, size), real-time operation, reliability, often without standard UI.

• Classification:

  1. Standalone: Single-function (e.g., calculator, printer).

  2. Real-Time: Must meet strict timing deadlines (e.g., industrial controller, anti-lock brakes).

  3. Networked: Connected to a network (e.g., smart thermostat, web server).

  4. Mobile: Battery-powered, portable (e.g., smartphones, wearables).

• Role of Microcontrollers: The heart of most embedded systems. Integrates CPU, memory (RAM/ROM), I/O ports, timers, ADC/DAC, communication interfaces on a single chip. Provides cost-effective, compact, low-power solution.

II. 8086 MICROPROCESSOR

A. Architecture

1. Functional Block Diagram: Two independent units:

   • Bus Interface Unit (BIU): Handles all bus operations (address generation, instruction fetch, read/write). Contains Instruction Pointer (IP), segment registers, address adder, instruction queue (6 bytes).

   • Execution Unit (EU): Executes instructions. Contains ALU, general-purpose registers (AX, BX, CX, DX), pointer/index registers (SP, BP, SI, DI), flag register. Does not access bus directly; fetches instructions from BIU's queue.

2. Register Organization:

   • General Purpose (16-bit): AX (Accumulator), BX (Base), CX (Count), DX (Data). Each can be used as two 8-bit registers (e.g., AH/AL).

   • Segment Registers (16-bit): CS (Code), DS (Data), SS (Stack), ES (Extra). Hold segment base addresses.

   • Pointer/Index: SP (Stack Pointer), BP (Base Pointer), SI (Source Index), DI (Destination Index).

   • Instruction Pointer (IP): Holds offset of next instruction in CS.

B. Memory Organization

1. Segmentation Concept: 1MB memory ($$\displaystyle 2^{20} $$ bytes) is divided into 64KB segments. A logical address = Segment:Offset (e.g., 2000:1234h).

2. Physical Address Calculation:

$$ \text{Physical Address} = (\text{Segment Register} \times 16) + \text{Offset} $$

> Example: `2000:1234h` → $$\displaystyle 2000h \times 10h = 20000h + 1234h = 21234h $$.

3. Even/Odd Bank Memory Organization:

   • Memory is organized as two banks: even-addressed bytes (D0-D7) and odd-addressed bytes (D8-D15).

   • Word access (16-bit): If offset is even, both banks accessed in one cycle. If odd, requires two bus cycles (first for low byte, second for high byte).

4. Advantages of Segmentation: Memory protection (via segment limits), modular programming (code/data/stack in separate segments), >64KB data structures possible via multiple segments.

C. Operating Modes

D. Timing Diagrams (Minimum Mode)

1. Memory Read Cycle (T1-T4):

   • T1: Address (20-bit) on address bus, ALE goes high (latch address), M/IO=High (memory), DT/R=High (read).

   • T2: Address bus floated (high-impedance), RD goes low, data bus driven by memory.

   • T3: Data valid on bus, DEN goes low (enable data bus buffer).

   • T4: RD, DEN go high, data latched by 8086. Wait states (TW) inserted between T3 & T4 if memory is slow (READY=0).

   Control Signals: RD (active low read), M/IO (memory vs I/O), DT/R (data transmit/receive direction), DEN (data bus enable).

E. Addressing Modes (8086)

[!TIP] Default Segments: CS for IP, SS for SP/BP, DS for others (except BP which defaults to SS).

F. Instruction Set (Summary)

• Data Transfer: MOV, PUSH/POP (stack), XCHG, XLAT (translate), LEA (load effective addr), LDS/LES (load far ptr).

• Arithmetic: ADD, ADC (add with carry), SUB, SBB (sub with borrow), INC/DEC, MUL/IMUL (unsigned/signed mult), DIV/IDIV, AAA (ASCII adjust), DAA (decimal adjust).

• Logical: AND, OR, XOR, TEST (and set flags), NOT, shift/rotate (SHL/SAL, SHR, SAR, ROL, ROR, RCL, RCR).

• Branch/Loop: JMP (near/far), CALL/RET (near/far), conditional jumps (JE, JNE, JL, JG, etc.), LOOP, LOOPE/LOOPNE.

• Flag Manip: STC/CLC (carry), STD/CLD (direction), STI/CLI (interrupt), SAHF/LAHF.

• String: MOVSB/MOVSW, CMPSB/CMPSW, SCASB/SCASW, LODSB/LODSW, STOSB/STOSW. Use REP prefix for repetition.

G. Flag Register (PSW)

Affected by ADD: CF, PF, AF, ZF, SF, OF. Unaffected: TF, IF, DF.

H. Interrupts

1. Hardware:

   • NMI (Non-Maskable): Type 2 interrupt. Cannot be disabled. For critical errors (parity, power fail).

   • INTR (Maskable): Level-triggered. Enabled only if IF=1. Requires external INTA cycle.

2. Software: INT n (Type n interrupt, 0-255). Example: INT 21h (DOS services).

3. Interrupt Response Sequence:

   1. Current CS:IP and Flags pushed onto stack.

   2. IF and TF cleared.

   3. CS:IP loaded from Interrupt Vector Table (IVT) at 00000h-003FFh. Each entry = 4 bytes (CS:IP).

   4. Transfer control to ISR.

4. IVT: Located at linear address 0. Contains 256 far pointers (CS:IP). Type n vector at n × 4.

5. ISR: Must end with IRET (return from interrupt).

6. Enable/Disable: STI (set IF), CLI (clear IF).

I. Assembly Language Programming (Examples)

• Add two 16-bit numbers:

  
  MOV AX, [NUM1]   ; Load first number
  
  ADD AX, [NUM2]   ; Add second
  
  MOV [RESULT], AX ; Store result
  
  

• Sort array (ascending, bubble sort):

  
  ; Assume CX = count, SI points to array
  
  MOV BX, CX
  
  DEC BX           ; Outer loop counter = N-1
  
  OUTER: MOV CX, BX
  
         LEA SI, ARRAY
  
  INNER: MOV AX, [SI]
  
         CMP AX, [SI+2]
  
         JBE SKIP
  
         XCHG AX, [SI+2]
  
         MOV [SI], AX
  
  SKIP: ADD SI, 2
  
         LOOP INNER
  
         DEC BX
  
         JNZ OUTER
  
  

• Find largest in array:

  
  LEA SI, ARRAY    ; SI = base addr
  
  MOV CX, N        ; count
  
  MOV AL, [SI]     ; Assume first is max
  
  DEC CX
  
  NEXT: INC SI
  
        CMP AL, [SI]
  
        JAE SKIP    ; Jump if AL >= [SI]
  
        MOV AL, [SI]
  
  SKIP: LOOP NEXT
  
  MOV MAX, AL
  
  

J. Memory Interfacing

1. Address Decoding:

   • Absolute Decoding: All address lines used to generate unique CS. Full decoding, no aliasing.

   • Partial Decoding: Some address lines ignored (don't cares). Simpler hardware but address aliasing (multiple addresses map to same chip).

2. Memory Mapping: Assigning specific address ranges to RAM, ROM, I/O devices.

3. Chip Select Logic: CS = f(A0-A19). Use decoders (e.g., 74LS138) or gates.

4. Interfacing Example: 32KB RAM (00000h-07FFFh)

   • Requires 15 address lines (A0-A14). A15-A19 = 0.

   • CS = A15' A14' A13' (active low) using 3-input NAND gate.

5. Memory Bank Organization: Even bank (D0-D7) enabled when A0=0; Odd bank (D8-D15) enabled when A0=1. Allows word access when offset even.

III. PROGRAMMABLE PERIPHERAL DEVICES

A. 8255 Programmable Peripheral Interface (PPI)

1. Block Diagram: Data Bus Buffer (8-bit), Control Logic, Port A, Port B, Port C (split into upper/lower).

2. Operating Modes:

   • Mode 0 (Simple I/O): Basic input/output, no handshaking. All ports can be input/output.

   • Mode 1 (Strobed I/O): Handshaking for Port A or B. Uses Port C bits for control (STB, IBF, OBF, ACK).

   • Mode 2 (Bidirectional Bus): Only Port A. Bidirectional data bus with handshaking (Port C provides control).

3. BSR Mode: Set/Reset individual bits of Port C. Control word format: D7=0, D6-D4=0, D3-D1=bit select, D0=set(1)/reset(0).

4. Control Word Format (I/O Mode):

   
   D7: 1 (I/O mode)
   
   D6-D5: Port A mode (00=Mode0, 01=Mode1, 1x=Mode2)
   
   D4: Port C upper (1=input, 0=output)
   
   D3-D2: Port B mode (same as A)
   
   D1: Port C lower (1=input, 0=output)
   
   D0: 1 (for Mode 1/2, Port B uses PC4-PC7 as control)
   
   

5. Interfacing with 8086: Connect to low/high byte data bus. I/O addresses assigned using A0, A1.

6. Applications:

   • Mode 1 Output: OBF goes low when data available, external device acknowledges with ACK.

   • Square Wave (BSR): Toggle a bit of Port C periodically using software delay loop.

B. 8254 Programmable Interval Timer (PIT)

1. Block Diagram: Three independent 16-bit counters (0,1,2), Read/Write Logic, Control Register.

2. Operating Modes:

   • Mode 0: Interrupt on terminal count (one-shot).

   • Mode 1: Programmable one-shot (hardware retriggerable).

   • Mode 2: Rate generator (periodic square wave).

   • Mode 3: Square wave generator (similar to 2, 50% duty cycle).

   • Mode 4: Software triggered strobe.

   • Mode 5: Hardware triggered strobe.

3. Control Word Format:

   
   D7-D6: Channel select (00=C0, 01=C1, 10=C2, 11=Read-back)
   
   D5-D4: Read/Write (00=latch, 01=LSB only, 10=MSB only, 11=LSB then MSB)
   
   D3-D1: Mode (001=Mode1, 010=Mode2, 011=Mode3, etc.)
   
   D0: BCD(0)/Binary(1)
   
   

4. Applications: Time delay (Mode 1), square wave generation (Mode 3), event counting (Mode 0).

C. 8257 DMA Controller

1. Register Organization:

   • DMA Address Registers (4): 16-bit, hold source/dest address for each channel.

   • Terminal Count Registers (4): 16-bit, lower 14 bits = byte count, upper 2 bits = mode (autoinit, address increment/decrement).

   • Mode Set Register: Channel priority (fixed/rotating), autoinitialize enable, timing (demand/block/single/cascade).

   • Command/Status Register: Read/write, priority, mask bits, terminal count status.

2. Operating Modes:

   • Demand: Transfer until DREQ low, then pause.

   • Single: One byte/word per DREQ.

   • Block: Entire block transferred once DREQ asserted.

   • Cascade: For cascading multiple 8257s.

3. Priority Schemes: Fixed (CH0>CH1>CH2>CH3) or Rotating (after service, channel moves to lowest priority).

4. Interfacing with 8086: Uses HOLD (request) and HLDA (acknowledge) signals. Takes control of address/data buses during transfer.

5. Initialization Example: Transfer 2KB (2048 bytes) from 75000h to channel 1. I/O ports at 70h (address), 80h (data).

   
   ; Assume 8257 addr ports: 70h (ch0-3 addr), 72h (ch0-3 TC), 74h (mode/cmd)
   
   MOV AL, 00h        ; Ch1 addr low byte
   
   OUT 71h, AL        ; Port 71h = ch1 addr low
   
   MOV AX, 75000h
   
   OUT 70h, AL        ; Ch1 addr high byte (A8-A15)
   
   MOV AL, AH
   
   OUT 70h, AL        ; Ch1 addr low byte (A0-A7)
   
   ; Set TC = 2048 (0800h)
   
   MOV AL, 00h
   
   OUT 73h, AL        ; Ch1 TC low
   
   MOV AL, 08h
   
   OUT 73h, AL        ; Ch1 TC high (mode=00, count=0800h)
   
   ; Mode set: Ch1, demand mode, write transfer, addr increment
   
   MOV AL, 42h        ; 01000010b: ch1=01, write=0, mode=00 (demand), inc addr=1
   
   OUT 74h, AL
   
   ; Unmask Ch1
   
   MOV AL, 0FDh       ; 11111101b (mask ch1=0)
   
   OUT 74h, AL
   
   

D. 8259A Programmable Interrupt Controller (PIC)

1. Block Diagram Components:

   • Interrupt Request Register (IRR): Holds pending interrupt requests from IR0-IR7.

   • In-Service Register (ISR): Holds interrupts currently being serviced.

   • Priority Resolver: Determines highest priority pending interrupt (considering masking, rotation).

   • Interrupt Mask Register (IMR): Masks interrupts (1=masked).

   • Control Logic: Generates INT to CPU, handles INTA cycles.

2. Operating Modes:

   • Fully Nested: Fixed priority (IR0 highest, IR7 lowest). New interrupt can't preempt higher priority ISR.

   • Special Fully Nested: Allows nested interrupts within same priority level (for cascaded systems).

   • Call Address Interval: 4-byte (8086/88) or 8-byte (8085) intervals between vectors.

   • Priority Rotation: Automatic (after ISR, priority rotates) or Specific (rotate to specific IR).

3. Initialization: Requires Initialization Command Words (ICW1-4) followed by Operation Command Words (OCW1-3).

4. Cascading: Master 8259A's IR2 connected to slave's INT. Master's CAS0-2 outputs select active slave.

E. 8251 USART

1. Block Diagram: Transmitter (parallel-to-serial), Receiver (serial-to-parallel), Baud Rate Generator, Control Logic.

2. Control Word Format:

   • Mode Instruction: Sync/async, character length (5-8 bits), stop bits (1, 1.5, 2), parity (enable/odd/even).

   • Command Instruction: TxEN (transmit enable), RxEN (receive enable), DTR, RTS, SBRK (send break), ER (error reset), RI/TI (read to clear).

3. Operation:

   • Asynchronous: Start bit, data bits, optional parity, stop bit(s). Independent clocks for Tx/Rx.

   • Synchronous: Clock shared, data transmitted continuously (no start/stop bits), sync characters.

4. Interfacing: Separate I/O ports for data (read/write), status (read), control (write). TxRDY and RxRDY status bits.

5. Serial Communication Basics: Baud rate = bits/sec. Start bit (0), data (LSB first), parity, stop bit (1). For 8N1: 10 bits per byte.

F. ADC and DAC Interfacing

1. 0808/0809 ADC (8-bit, 8-channel):

   • Block: Multiplexer (select channel), Comparator, Successive Approximation Register (SAR), Control Logic.

   • Operation: START pulse initiates conversion, EOC (End of Conversion) goes low when done. ALE latches address (channel select).

2. Interfacing ADC with 8086:

   • Signals: CS (chip select), RD (read data), WR (start conversion), CLK (external clock), EOC (status).

   • Procedure:

     1. Output channel address to ADC address lines (via latch).

     2. Pulse WR (low then high) to start conversion.

     3. Poll EOC or wait for interrupt.

     4. Pulse RD to read converted data from data bus.

3. DAC Interfacing (e.g., 0800): Write digital value to DAC input register. Output analog voltage proportional to input. Used for waveform generation (sine, square) by updating value periodically.

4. Applications: Data acquisition (ADC), control systems (DAC), waveform generation, digital oscilloscopes.

IV. ADVANCED x86 PROCESSORS

A. 80286

• 16-bit data bus, 24-bit address bus (16MB memory).

• Protected Mode: Memory management via descriptor tables (GDT/LDT), privilege levels (ring 0-3), hardware task switching.

• Instruction Set: Added PUSH/POP of all registers, INS/OUTS string I/O, BOUND array check.

• Limitations: No paging, 24-bit addressing only in protected mode, no virtual 8086 mode.

B. 80386

• 32-bit registers (EAX, EBX, etc.), 32-bit address bus (4GB linear address space).

• Paging: 4KB pages, two-level page tables (Page Directory, Page Table). Enables virtual memory.

• Virtual 8086 Mode: Run multiple 8086 programs concurrently under protected mode OS.

• Multi-tasking: Hardware support for task state segment (TSS), task gates.

• New Instructions: BSF/BSR (bit scan), BT/BTS/BTR/BTC (bit test/ manipulate), MOVZX/MOVSX (zero/sign extend).

C. 80486 vs Pentium

Pentium U/V-pipe: U-pipe can execute any instruction; V-pipe limited to simple integer ops. Both pipes work in parallel if instructions are independent.

V. 8051 MICROCONTROLLER

A. Architecture

1. Block Diagram: CPU (ALU, Accumulator, B register), On-chip Memory (4KB ROM/EPROM, 128/256 RAM), I/O Ports (P0-P3), Timers (T0, T1), Serial (UART), Interrupt Control.

2. Memory Organization:

   • Program Memory: On-chip (0000h-0FFFh) if EA=1; Off-chip (0000h-FFFFh) if EA=0. PSEN active for off-chip fetch.

   • Data Memory: On-chip RAM (00h-7Fh) + SFRs (80h-FFh). Off-chip accessed via MOVX (up to 64KB).

   • SFRs: Special Function Registers at 80h-FFh (e.g., P0=80h, P1=90h, TCON=88h).

3. Pin Diagram Functions:

   • P0.0-P0.7: Multiplexed AD0-AD7 (address/data) for external memory. Open-drain, need pull-ups.

   • P1.0-P1.7: Pure I/O, internal pull-up.

   • P2.0-P2.7: A8-A15 when accessing external memory; otherwise I/O.

   • P3.0-P3.7: I/O with alternate functions:

     • P3.0: RXD (serial input)

     • P3.1: TXD (serial output)

     • P3.2: INT0 (external interrupt 0)

     • P3.3: INT1 (external interrupt 1)

     • P3.4: T0 (timer 0 external input)

     • P3.5: T1 (timer 1 external input)

     • P3.6: WR (external memory write strobe)

     • P3.7: RD (external memory read strobe)

   • Control Pins: ALE (address latch enable), PSEN (program store enable), RST (reset), EA (external access), XTAL1/2 (crystal), VSS/VCC.

B. Register Organization

• General Purpose: R0-R7 (banked, 4 sets in RAM 00h-1Fh).

• Accumulator (A): Primary operand for ALU operations.

• B Register: Used for MUL/DIV (holds high byte of product/quotient).

• Data Pointer (DPTR): 16-bit (DPL=82h, DPH=83h) for external memory addressing.

• Program Counter (PC): 16-bit, points to next instruction.

• Stack Pointer (SP): 8-bit, points to internal RAM (default 07h). PUSH/POP use indirect addressing via @R0/@R1.

• PSW (Program Status Word, D0h):

  
  Bit 7: CY (Carry)
  
  Bit 6: AC (Aux Carry)
  
  Bit 5: F0 (Flag 0, user)
  
  Bit 4-3: RS1, RS0 (Register Bank Select)
  
  Bit 2: OV (Overflow)
  
  Bit 1: - (Unused)
  
  Bit 0: P (Parity)
  
  

C. Special Function Registers (SFRs)

D. Memory Access

• On-chip vs Off-chip Program: EA pin high = on-chip ROM (0000h-0FFFh); EA low = off-chip only. PSEN active for off-chip fetch.

• External Program Access Sequence: ALE latches address from P0/P2, PSEN low, data read from P0.

• External Data Access (MOVX): Uses RD/WR signals. DPTR or @R0/@R1 for address.

E. I/O Ports

• Structure: Quasi-bidirectional (internal pull-up, can be written 1 to read, 0 to drive low). P0 is open-drain (external pull-up needed).

• Alternate Functions (P3): See pin diagram above.

• Driving Capability: Can sink/source ~1.6mA (TTL compatible).

F. Addressing Modes (8051)

G. Instruction Set Overview

• Data Transfer: MOV (register, direct, indirect, immediate), MOVC (code memory), MOVX (external memory), PUSH/POP, XCH/XCHD.

• Arithmetic: ADD, ADDC, SUBB, INC, DEC, MUL/DIV (unsigned), DA (decimal adjust for BCD).

• Logical: ANL, ORL, XRL (byte/bit), CLR, CPL, SETB (bit).

• Branch: JMP (absolute LJMP, relative SJMP, indirect JMP @A+DPTR), CALL/RET/RETI, conditional jumps (JZ, JNZ, JC, JNC, JB, JNB, JBC).

• Bit Manipulation: SETB, CLR, CPL, JB, JNB, JBC.

• Rotate/Swap: RL, RR, RLC, RRC, SWAP (swap nibbles of A).

H. Interrupts

1. Sources:

   • External: INT0 (P3.2, vector 0003h), INT1 (P3.3, vector 0013h).

   • Timer: TF0 (timer 0 overflow, 000Bh), TF1 (timer 1 overflow, 001Bh).

   • Serial: RI (receive, 0023h), TI (transmit, 0023h).

2. Interrupt Enable (IE, A8h):

   • EA (global enable), ES (serial), ET1 (timer1), EX1 (int1), ET0 (timer0), EX0 (int0).

3. Interrupt Priority (IP, B8h): PS, PT1, PX1, PT0, PX0. 1=high priority.

4. Vector Addresses: Fixed locations in on-chip ROM (0000h-002Bh). All same address (0023h) for RI/TI → must check flags in ISR.

5. Sequence: Interrupt request → priority resolution → LCALL to vector → ISR → RETI (restore PSW, PC).

I. Timers/Counters

1. Structure: 16-bit (THx, TLx). Mode set by TMOD.

2. Modes:

   • Mode 0: 13-bit timer/counter (THx 8 bits, TLx lower 5 bits).

   • Mode 1: 16-bit timer/counter.

   • Mode 2: 8-bit auto-reload (TLx counts, THx holds reload value).

   • Mode 3: Timer 0 split into two 8-bit timers; Timer 1 stopped (can be used as baud rate generator).

3. Programming: Set TMOD, load count to THx/TLx, start (TRx=1), wait for TFx=1 or interrupt.

J. Serial Communication

1. UART Operation: Asynchronous, full-duplex. Start bit (0), 8 data bits (LSB first), optional parity, stop bit (1).

2. SCON (98h):

   • SM0, SM1: Mode select (00=Mode0, 01=Mode1, 10=Mode2, 11=Mode3).

   • SM2: Multiprocessor enable (Mode2/3).

   • REN: Receive enable.

   • TB8, RB8: 9th data bit (Mode2/3).

   • TI: Transmit interrupt flag (set when SBUF empty).

   • RI: Receive interrupt flag (set when byte received).

3. SBUF (99h): Write to transmit, read to receive.

4. Modes:

   • Mode 0: Synchronous shift register (baud rate = fosc/12).

   • Mode 1: 8-bit UART, variable baud rate (from Timer1 overflow).

   • Mode 2/3: 9-bit UART, fixed (Mode2) or variable (Mode3) baud.

K. Assembly Examples

• Swap nibbles of A: SWAP A

• Timer delay (Mode1):

  
  MOV TMOD, #01h   ; Timer0 Mode1
  
  MOV TH0, #HIGH(65536-50000) ; 50ms @ 12MHz
  
  MOV TL0, #LOW(65536-50000)
  
  SETB TR0         ; Start timer
  
  WAIT: JNB TF0, WAIT ; Wait for overflow
  
  CLR TR0
  
  CLR TF0
  
  

• External interrupt (INT0) to toggle P1.0:

  
  ORG 0003h        ; INT0 vector
  
  LJMP ISR_INT0
  
  ORG 0100h
  
  MAIN: SETB IT0   ; Edge triggered
  
        SETB EX0   ; Enable INT0
  
        SETB EA    ; Global enable
  
        SJMP $
  
  ISR_INT0: CPL P1.0
  
            RETI
  
  

VI. SYSTEM DESIGN AND APPLICATIONS

A. I/O Mapped vs Memory Mapped I/O

B. Bus Interfacing

• Address Bus: A0-A19 (8086), A0-A23 (80386+). Unidirectional from CPU.

• Data Bus: D0-D15 (8086), D0-D31 (80386+). Bidirectional.

• Control Bus: RD, WR, M/IO, ALE, READY, HOLD/HLDA, INTA, etc.

• Bus Buffering/Isolation: Use 8282 (address latch) or 74LS373 for address bus; 8286 or 74LS245 for data bus (transceivers) to isolate and drive heavy loads.

• Bus Arbitration: In maximum mode, 8289 Bus Arbiter manages HOLD/HLDA for multi-processor systems.

C. Designing Memory Maps

1. Assign address ranges to RAM, ROM, I/O based on size and constraints.

2. Use decoders (e.g., 74LS138) to generate CS from high-order address lines.

3. Example: Map 64KB RAM (00000h-0FFFFh), 32KB ROM (80000h-87FFFh), I/O ports (C000h-C0FFh).

   • RAM: CS_RAM = A15' (since A15=0 for 00000h-07FFFh? Actually 64KB needs A16=0 → CS = A16').

   • ROM: CS_ROM = A15 A14 A13' (for 80000h-87FFFh, A15=1, A14=0, A13=0? Check: 80000h=1000 0000 0000 0000 0000, so A19-A15=10000? Better: 32KB = 8000h bytes → addresses 80000h-87FFFh → A19-A15=10000? Let's recalc: 80000h in binary: 1000 0000 0000 0000 0000 → A19=1, A18=0, A17=0, A16=0, A15=0? Actually 20-bit address: A19-A0. 80000h = 1000 0000 0000 0000 0000₂ → A19=1, A18=A17=A16=A15=0. So CS_ROM = A19 A18' A17' A16' A15'? That's 1 output for 32KB block. Simpler: Use A19-A15 as input to decoder, enable one output for range where these bits = 10000₂? Actually 80000h-87FFFh is 32KB, so A19=1, A18=A17=A16=A15=0? 87FFFh = 1000 0111 1111 1111 1111 → A19=1, A18=0, A17=0, A16=0, A15=1? Wait, 80000h to 87FFFh is 8000h addresses. 80000h = 2^19 = 524288. 87FFFh = 524288 + 32767 = 557055. In binary: 80000h = 1000 0000 0000 0000 0000 (A19=1, rest 0). 87FFFh = 1000 0111 1111 1111 1111 (A19=1, A18=0, A17=0, A16=0, A15=1? Let's compute: 80000h + 7FFFh = 87FFFh. 7FFFh = 0111 1111 1111 1111. So A19=1, A18=0, A17=0, A16=0, A15=0? Actually 80000h has bits 19-15: 10000₂? 80000h / 2^15 = 80000h / 8000h = 10h? Let's do: 80000h = 524288 decimal. 2^15 = 32768. 524288 / 32768 = 16. So A19-A15 = 10000₂? 16 in binary is 10000, so A19=1, A18=0, A17=0, A16=0, A15=0? That's 5 bits: A19 A18 A17 A16 A15. 10000₂ means A19=1, others 0. So for 80000h-87FFFh, A19=1, A18=0, A17=0, A16=0, A15 varies? Actually 80000h to 87FFFh covers A19=1, A18=0, A17=0, A16=0, and A15-A0 from 0000h to 7FFFh. So A15 can be 0 or 1? 7FFFh has A15=0? 7FFFh = 0111 1111 1111 1111, so A15=0? Wait, A15 is bit 15 (value 2^15=32768). 7FFFh = 32767, so A15=0. But 8000h = 32768, so A15=1. So range 80000h-87FFFh includes addresses with A15=0 and A15=1? Actually 80000h = 8000h * 2^15? Let's map: 20-bit address: A19 A18 A17 A16 A15 A14 ... A0. 80000h = 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0? That's 20 bits: 1 followed by 19 zeros? 2^19 = 524288 = 80000h. So A19=1, A18-A0=0. 87FFFh = 80000h + 7FFFh = 524288 + 32767 = 557055. 557055 in hex: 87FFFh. Binary: 1000 0111 1111 1111 1111. So bits: A19=1, A18=0, A17=0, A16=0, A15=1? Actually 1000 0111 ...: A19=1, A18=0, A17=0, A16=0, A15=1? Let's count: 20 bits: positions 19 to 0. 1000 0111 1111 1111 1111: group: 1 000 0111 1111 1111 1111. So A19=1, A18=0, A17=0, A16=0, A15=1? Wait, after A19=1, next three are A18,A17,A16 = 000, then A15-A0 = 1111 1111 1111 1111? That would be A15=1? Actually "000 0111" means A18=0, A17=0, A16=0, then A15=0? Let's write properly: 1000 0111 1111 1111 1111 in 20 bits: 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1? That's 20 bits: bit19=1, bit18=0, bit17=0, bit16=0, bit15=0? I'm confused. Better: 87FFFh = 0x87FFF. Convert to binary: 8=1000, 7=0111, F=1111, F=1111, F=1111. So 1000 0111 1111 1111 1111. That's 20 bits: positions 19-16: 1000, positions 15-12: 0111, positions 11-0: 1111 1111 1111. So A19=1, A18=0, A17=0, A16=0, A15=0? Actually 1000 means A19=1, A18=0, A17=0, A16=0. Then next nibble 0111: A15=0, A14=1, A13=1, A12=1. So A15=0. So for 80000h-87FFFh, A19=1, A18=0, A17=0, A16=0, and A15-A0 from 0000h to 7FFFh. So A15 can be 0 or 1? 7FFFh has A15=0? 7FFFh = 0111 1111 1111 1111, so A15=0 (bit15 is 0 for 32767). But 8000h = 1000 0000 0000 0000, so A15=1. So range includes both A15=0 and A15=1? Actually 80000h to 87FFFh: 80000h has A15=0 (since 80000h / 2^15 = 16, remainder 0? Let's compute: 80000h = 524288. 2^15=32768. 524288 / 32768 = 16 exactly, so A15=0? Wait, A15 is bit 15, value 32768. If address >= 32768, A15=1? Actually in 20-bit address, A15 is bit 15 (2^15=32768). So addresses 0-32767 have A15=0; 32768-65535 have A15=1. But 80000h is 524288, which is > 32768, so A15=1? Let's check: 32768 decimal = 8000h. So any address >= 8000h has A15=1? But 80000h is way larger. Actually A15 is bit 15 of the 20-bit address. The address is A19...A0. A15 is the 16th bit from LSB? Bit positions: A0 (LSB), A1, ..., A19 (MSB). A15 is the 16th bit (value 2^15=32768). So for address 524288 (80000h), in binary: 1000 0000 0000 0000 0000. Bits: A19=1, A18=0, A17=0, A16=0, A15=0? Because after A19=1, we have 19 zeros. So A15 is the 5th bit from MSB? Let's index: A19 (bit19), A18(18), A17(17), A16(16), A15(15), ... A0(0). So for 80000h, bits 19-0: 1 followed by 19 zeros. So A19=1, A18=0, A17=0, A16=0, A15=0, ..., A0=0. So A15=0. For 87FFFh: 1000 0111 1111 1111 1111. Bits: A19=1, A18=0, A17=0, A16=0, A15=0? Actually the next after A16=0 is A15: the next bit is the first of "0111"? The binary is 1000 0111 1111 1111 1111. Group as 4-bit: 1000 0111 1111 1111 1111. So bits 19-16: 1000 → A19=1, A18=0, A17=0, A16=0. Bits 15-12: 0111 → A15=0, A14=1, A13=1, A12=1. So A15=0. So for entire range 80000h-87FFFh, A19=1, A18=0, A17=0, A16=0, and A15-A0 from 0000h to 7FFFh. So A15 is 0 for all? 7FFFh has A15=0? 7FFFh = 0111 1111 1111 1111, so A15=0. So indeed A15=0 throughout. So CS_ROM = A19 A18' A17' A16' (since A19=1, others 0). That's a 4-to-1 decoder enable? Actually we want active low CS. So CS_ROM = A19' + A18 + A17 + A16? No, we want CS low when A19=1 and A18=0, A17=0, A16=0. So CS_ROM = A19 AND (A18') AND (A17') AND (A16'). That's a 4-input AND gate. Or use 74LS139 (2-to-4 decoder) with A19 as enable? Better: Use A19 as chip enable (active high) and decode A18-A16 with 3-to-8 decoder. But for simplicity in exam, we can say: For 32KB ROM at 80000h-87FFFh, use A19 as enable (since block starts at 2^19), and A18-A16 all 0 → decode with 3-input NAND: CS = A19' + A18 + A17 + A16? Actually active low: CS = NOT(A19 AND NOT A18 AND NOT A17 AND NOT A16) = A19' + A18 + A17 + A16. But that would be low only when A19=1 and A18=A17=A16=0. So yes.

   • I/O: CS_IO = A15 A14 A13 A12 A11 A10 A9 A8' for C000h-C0FFh? C000h = 1100 0000 0000 0000 0000. So A19-A12 = 1100 0000? Actually C000h in 20-bit: 1100 0000 0000 0000 0000. So A19=1, A18=1, A17=0, A16=0, A15=0, A14=0, A13=0, A12=0? Let's compute: C000h = 12 * 4096 = 49152. Binary: 1100 0000 0000 0000. That's 16 bits. For 20-bit, it's 0000 1100 0000 0000 0000? Actually 20-bit address: C000h = 0000 1100 0000 0000 0000? Because 2^16=65536, C000h=49152 < 65536, so A19-A16=0. So A19=0, A18=0, A17=0, A16=0, A15=1? Wait, 49152 / 32768 = 1.5, so A15=1? 32768 is 8000h. 49152 - 32768 = 16384 = 4000h. So address: A15=1 (32768), A14=0? 16384 is 4000h, so A14=1? Actually 16384 = 2^14, so A14=1. So C000h = 1100 0000 0000 0000 in 16-bit? That's bits 15-0: 1100 0000 0000 0000. So A15=1, A14=1, A13=0, A12=0, ..., A0=0. So for 20-bit, A19-A16=0. So CS_IO = A15' A14' A13' ...? For C000h-C0FFh, we need A15=1, A14=1, A13=0, A12=0, and A11-A8=0? C000h: A15=1, A14=1, A13=0, A12=0, A11=0, A10=0, A9=0, A8=0. C0FFh: same but A7-A0=11111111. So condition: A15=1, A14=1, A13=0, A12=0, A11=0, A10=0, A9=0, A8=0. So CS_IO = A15 AND A14 AND NOT A13 AND NOT A12 AND NOT A11 AND NOT A10 AND NOT A9 AND NOT A8. That's many gates. Usually we use decoder for high bits.

4. Example: 32KB RAM with 8086 (from past paper): Address range? 32KB = 8000h bytes. Can be mapped at any 32KB boundary (multiple of 8000h). Suppose at 00000h-07FFFh. Then A15=0 (since 07FFFh < 8000h). So CS_RAM = A15' (active low if CS active low). Or use A15 as chip enable (active high) and invert.

D. Interfacing Multiple Peripherals

• Use address decoding with decoders (74LS138) to assign unique I/O addresses.

• Ensure no address conflict by proper decoding (e.g., use A0-A2 for 8255 ports, A3-A4 for 8254, etc.).

• Cascading: For 8259A, connect slave INT to master IR2, master CAS0-2 to slave CAS0-2.

E. Applications

1. 8086: General-purpose computing, DOS-based systems.

2. 8051: Embedded control (appliances, automotive, toys).

3. ADC Interfacing: Data acquisition systems (temperature monitoring, digital oscilloscope).

4. USART: Communication systems (modem, RS-232, GPS).

5. Industrial Automation: PLCs, motor speed control (using DAC + timer).

6. Consumer Electronics: Microwave oven controller (8051), keyboard/mouse (8255).

END OF UNIT 1 NOTES