Simulation Lab (EC-406) - Unit 2 Short Notes

UNIT 2: Advanced Simulation Techniques & Analysis

2.0 Introduction to Unit 2 & Prerequisites

• Recap from Unit 1: Basic circuit creation, component placement, wiring, running a simple simulation (e.g., DC operating point, transient), and viewing waveforms.

• Primary Software Platform: This unit's concepts are universal but implemented in specific tools. Common platforms include:

  • SPICE-based: LTspice, PSpice, NGSpice (for analog/mixed-signal).

  • MATLAB/Simulink: For system-level, control, and signal processing simulations.

  • ModelSim/Questa: For HDL (VHDL/Verilog) digital simulation.

  • NS-3: For network simulations.

• Learning Objectives: Transition from running simulations to designing, configuring, and verifying complex systems. Focus on model parameterization, advanced analysis types, troubleshooting convergence, and systematic validation.

2.1 Advanced Simulation Setup & Environment Configuration

• Workspace & Project Management: Organize files into dedicated project folders. Use hierarchical blocks/schematics to manage complexity.

• Global Simulation Parameters:

  • Temperature: Affects semiconductor models (.TEMP).

  • Tolerances: Define global component mismatch (.OPTIONS).

  • Default Units: Ensure consistency (e.g., u for micro, m for milli).

• Library Management:

  • Add custom .lib files (SPICE models) and symbol libraries.

  • Understand model file paths and precedence.

• Solver Configuration & Convergence:

  • Solver Type: Choose between implicit (Gear, Trapezoidal) and explicit methods.

  • Convergence Aids: Adjust reltol (relative tolerance), abstol (absolute tolerance), vntol (voltage tolerance). Use ITL1 (iteration limit for nonlinear).

• Simulation Profiles: Save/load complete sets of analysis parameters (e.g., "Transient_10ms", "AC_Sweep_1MHz") for repeatability.

[!TIP] Exam Focus: Be prepared to explain why a simulation fails to converge (e.g., stiff circuit, poor initial guess) and what specific solver options to tweak.

2.2 Component Modeling & Parameterization

• Built-in Models: Understand model parameters (e.g., IS, BF for BJT; VTO, KP for MOSFET). Access via component attributes.

• Sub-circuits & Hierarchical Design:

  • Create reusable blocks (.SUBCKT in SPICE, Subsystem in Simulink).

  • Use .ENDS to define boundaries.

• Parameterization:

  • .PARAM Statements: Define global variables (.PARAM Rload=1k).

  • Sweeping: Use .STEP command (SPICE) or "Sweep" tool (Simulink) to vary a parameter (e.g., R1 from 1k to 10k in 1k steps).

  • Example (SPICE): .STEP PARAM Rload LIST 1k 2k 5k 10k

• Behavioral Modeling:

  • Use voltage/current sources with PWL (Piecewise Linear) or SINE/PULSE expressions.

  • Example (SPICE Vsource): V1 in 0 PWL(0 0 1n 0 1.1n 5 2n 5)

• Stimulus Sources: Configure pulse parameters (Vinitial, Von, TD, TR, TF, PW, PER).

2.3 Types of Simulations & Analysis (Expanded)

[!TIP] Common Pitfall: In AC Analysis, results are complex (magnitude/phase). db(V(out)) gives magnitude in dB, ph(V(out)) gives phase in degrees. Never interpret AC magnitude as time-domain amplitude.

2.4 Probes, Measurements, and Data Analysis

• Virtual Instruments: Use built-in scopes, multimeters, logic analyzers. Configure timebase, triggers, and channels.

• Simulation Probes:

  • Voltage Probe: V(node) or click on wire.

  • Current Probe: I(source) or click on device pin (with polarity).

  • Power Probe: P(device) (e.g., P(Q1)).

• Expression-Based Measurements:

  • Gain: V(out)/V(in) or db(V(out)/V(in)).

  • Bandwidth: Find frequency where db(V(out)/V(in)) = -3dB.

  • Rise/Fall Time: Use cursor measurements or trise(V(out), 10%, 90%).

  • Power Dissipation: P(Vdd) or sum of P(device).

  • Total Harmonic Distortion (THD): THD(V(out), fundamental_freq).

• Data Export: Save waveform data as .txt/.csv for analysis in MATLAB, Python, or Excel. Use WRITE command (SPICE) or "Export Data" feature.

2.5 Troubleshooting & Convergence Issues

• Common Causes:

  1. Stiff Circuit: Nodes with vastly different time constants (e.g., capacitor across a small resistor).

  2. Poor Initial Guess: Unbiased circuit starting at 0V.

  3. Missing DC Path: Floating node (no DC connection to ground).

  4. Ideal Components: Unlimited voltage/current sources causing singular matrix.

• Diagnostic Techniques:

  • Run a DC Operating Point analysis first. Check for "Node is floating" or "Singular matrix" errors.

  • Isolate Sub-circuits: Disconnect blocks to find the problematic section.

• Convergence Aids (SPICE):

  • Add a tiny conductance to ground: G=0 source or R=1G resistor from floating node to ground.

  • Set Initial Conditions (IC): Manually set node voltages/device currents.

  • Use UIC (Use Initial Conditions) in transient analysis to skip DC operating point calculation.

  • Relax tolerances: OPTIONS RELTOL=0.01.

  • Limit maximum step size in transient (TMAX).

[!TIP] Golden Rule: If a circuit won't simulate, first ensure every node has a DC path to ground and add a high-value resistor (1GΩ) from any truly floating node to ground.

2.6 Design Verification & Validation Techniques

• Cross-Checking: Compare simulation results with hand calculations, datasheet specs (e.g., op-amp GBW, MOSFET Idsat), and SPICE model documentation.

• Corner Case Analysis: Simulate at process corners (e.g., TT, FF, SS for CMOS) and temperature extremes.

• Automated Test Benches:

  • Create a dedicated schematic with input stimuli and measurement probes.

  • Use assertions (in Verilog/SystemVerilog) or measurement scripts (SPICE .MEAS statements) to automatically flag failures.

  • Example (SPICE .MEAS): .MEAS TRAN t_delay TRIG V(in)=2.5 RISE=1 TARG V(out)=2.5 RISE=1

• Regression Testing: Save key simulation results and re-run after any design change to ensure no degradation.

2.7 Introduction to Mixed-Signal & System-Level Simulation

• Co-simulation: Analog SPICE netlist + digital HDL (VHDL/Verilog) model.

  • Interface: Use A2D (Analog-to-Digital) and D2A (Digital-to-Analog) converter models.

• Sample Time & Solver:

  • Analog Solver: Continuous, variable-step (e.g., for SPICE).

  • Digital Solver: Discrete, event-driven (e.g., for HDL).

  • Synchronization: The analog solver provides values at digital sample times. Set appropriate sample time for digital blocks.

• Example System: Simulate a PWM generator (digital) driving an LC filter (analog) and measure ripple.

2.8 Lab Report Preparation & Documentation for Simulations

• Essential Sections:

  1. Objective: What circuit/analysis is being verified?

  2. Circuit Diagram: Annotated with key component values and node names.

  3. Simulation Setup: Specify software, analysis type, simulation commands (.TRAN 1u 10m), and critical parameters (tolerance, temperature).

  4. Results: Clear, labeled graphs/tables. Use cursors to mark key points (rise time, frequency).

  5. Discussion: Compare sim vs. theory. Explain discrepancies (model limitations, idealizations). Analyze trends.

  6. Conclusion: State if design objectives were met.

• Best Practices:

  • Annotate waveforms directly on plots (e.g., "f_c = 1.2 MHz").

  • Include simulation log excerpts if convergence was an issue and how it was fixed.

  • Document all assumptions (e.g., "ideal op-amp model used").

2.9 Advanced Topics & Software-Specific Features

(Tailor to your specific lab software - examples below)

• For SPICE-based Tools (LTspice/PSpice):

  • .FOUR Command: Perform Fourier analysis on transient data to find harmonic content (THD).

  • .STEP + .MEAS: Automate measurement across multiple runs and generate tabulated results.

  • ** Behavioral Sources (B):** Define complex sources using mathematical expressions (e.g., B1 out 0 V = sin(2*pi*1k*time)).

  • Sub-circuit Netlists: Create and include external .sub files for complex models (e.g., a microcontroller model).

• For MATLAB/Simulink:

  • Simscape: Physical modeling (electrical, mechanical). Use fundamental components (resistors, gears) instead of transfer functions.

  • Stateflow: Model event-driven logic and state machines for control systems.

  • Code Generation: Use Simulink Coder to generate C code from your model for embedded targets.

  • Model Advisor: Run automated checks for model compliance and best practices.

• For ModelSim/Questa (HDL):

  • Testbench Coding: Write structured testbenches with clock generation, reset, stimulus, and self-checking using assert.

  • Waveform Viewer: Use virtual buses, radix formatting (hex, binary), and find time between events.

  • Coverage: Collect code/functional coverage to verify testbench completeness.

[!TIP] Final Exam Strategy: You may be asked to write a short simulation command or configure an analysis. Know the syntax for your specific tool (e.g., .TRAN in SPICE vs. sim('stop_time') in Simulink). Practice writing a complete .STEP + .MEAS command sequence for a simple parametric sweep.