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AD-503 (C) · Computer Org. & Architecture/Quick Revision Short Notes

Computer Org. & Architecture (AD-503 (C)) - Unit 4 Short Notes

How unit 4 is examined

This unit covers main memory (RAM, ROM), secondary storage, cache memory, virtual memory and memory management hardware. None of these topics was asked in the supplied papers, so every topic is taught in full but kept short so it can be answered if it appears this year.

Main memory-RAM, ROM

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Not asked since 2022</span>

Definition. <mark>Main memory is the primary memory that the CPU accesses directly; RAM is volatile read-write memory and ROM is non-volatile read-only memory.</mark>

Key points.

  1. RAM (random access memory) loses its contents when power is switched off, and it holds the programs and data currently being executed.
  2. Static RAM (SRAM) stores each bit in a flip-flop of about six transistors, so it is very fast and needs no refresh, but it is costly and bulky, and is therefore used for cache.
  3. Dynamic RAM (DRAM) stores each bit as charge on a capacitor, so it must be refreshed every few milliseconds; it is cheaper and denser and is used for main memory.
  4. ROM (read only memory) keeps its contents without power and stores permanent programs such as the BIOS boot loader.
  5. ROM types are mask ROM (programmed at the factory), PROM (programmed once by the user), EPROM (erased by ultraviolet light) and EEPROM (erased electrically); flash memory is a block-erasable EEPROM.
  6. A memory chip of $2^n$ words needs $n$ address lines, and the address bus width fixes the maximum memory size.
Feature SRAM DRAM
Cell Flip-flop Capacitor plus transistor
Speed Faster Slower
Refresh Not needed Needed
Cost and density Costly, low density Cheap, high density
Use Cache Main memory

Secondary Memory –Magnetic Tape, Disk, Optical Storage

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Definition. <mark>Secondary memory is non-volatile, high-capacity and slower storage that holds programs and data permanently and is reached through the I/O system.</mark>

Key points.

  1. Magnetic tape stores data in tracks on a plastic tape and is accessed sequentially, so it is cheap and suited only to backup and archives.
  2. A magnetic disk stores data on rotating platters coated with magnetic material; each surface is divided into concentric tracks and each track into sectors, and a set of tracks at the same radius forms a cylinder.
  3. Disk access time is the sum of seek time (moving the head to the track), rotational latency (waiting for the sector) and transfer time.
  4. Average rotational latency is half a rotation: at 7200 rpm it is $\frac{60}{7200}\times\frac{1}{2} \approx 4.17$ ms.
  5. Optical storage such as CD, DVD and Blu-ray is read by a laser that detects pits and lands; CD-ROM is read-only, CD-R is write-once and CD-RW is rewritable.
  6. Disk and optical media give direct access, while tape gives only serial access.

Example. Seek 8 ms, latency 4.17 ms and transfer 0.1 ms give an access time of $8 + 4.17 + 0.1 =$ 12.27 ms.

Medium Access Typical use
Magnetic tape Sequential Backup, archive
Magnetic disk Direct Main storage
Optical disc Direct Distribution of software and media

Cache Memory: Cache Structure and Design, Mapping Scheme, Replacement Algorithm, Improving Cache Performance

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Definition. <mark>Cache memory is a small, fast memory placed between the CPU and main memory that holds recently used blocks, so that the average access time is close to the cache speed.</mark>

Diagram.

<figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u4-01" viewBox="0 0 603 80" width="603" height="80" role="img" aria-label="Memory hierarchy. CPU, cache, main memory and disk; speed and cost per bit fall to the right while size grows."><style>#dsfig-u4-01 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u4-01 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u4-01 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u4-01 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u4-01 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u4-01 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u4-01 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u4-01 .t{fill:#16181D;font-weight:500}#dsfig-u4-01 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u4-01 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u4-01 .dot{fill:#16181D}#dsfig-u4-01 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u4-01 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u4-01 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u4-01 .ah{fill:#454C5A}#dsfig-u4-01 .ah.hi{fill:#2340B8}#dsfig-u4-01 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u4-01 .wl .t{font-size:12px;font-weight:700}#dsfig-u4-01 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u4-01 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u4-01 .e{stroke:#B1B7C3}html.dark #dsfig-u4-01 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u4-01 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u4-01 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u4-01 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u4-01 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u4-01 .t{fill:#E6E8ED}html.dark #dsfig-u4-01 .t.inv{fill:#0F1115}html.dark #dsfig-u4-01 .kd{stroke:#E6E8ED}html.dark #dsfig-u4-01 .dot{fill:#E6E8ED}html.dark #dsfig-u4-01 .ann{fill:#8FA3FF}html.dark #dsfig-u4-01 .lbl{fill:#858D9C}html.dark #dsfig-u4-01 .ptr{fill:#8FA3FF}html.dark #dsfig-u4-01 .ah{fill:#B1B7C3}html.dark #dsfig-u4-01 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u4-01 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u4-01 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u4-01 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah9" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh9" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M61,40 L191,40" marker-end="url(#ah9)" marker-start="url(#ah9)"/><path class="e" d="M233,40 L363,40" marker-end="url(#ah9)" marker-start="url(#ah9)"/><path class="e" d="M405,40 L528,40" marker-end="url(#ah9)" marker-start="url(#ah9)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">Cac</text><circle class="n" cx="384" cy="40" r="18"/><text class="t" x="384" y="40" dy=".35em" text-anchor="middle">MM</text><rect class="n" x="531" y="25" width="50" height="30" rx="15"/><text class="t" x="556" y="40" dy=".35em" text-anchor="middle">Disk</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Memory hierarchy. CPU, cache, main memory and disk; speed and cost per bit fall to the right while size grows.</figcaption></figure>

Key points.

  1. A hit means the requested word is found in the cache, and a miss means the block must be fetched from main memory; hit ratio $h$ = hits divided by total accesses.
  2. Cache works because of locality of reference: temporal locality (a used item is used again soon) and spatial locality (nearby items are used next).
  3. Average access time is $T_{avg} = h\,T_c + (1-h)\,T_m$, where $T_c$ is cache time and $T_m$ is main memory time.
  4. Direct mapping places main memory block $j$ only in line $j \bmod N$ of the cache, which is simple and fast but causes conflict misses when two blocks share a line.
  5. Fully associative mapping lets any block go into any line, which avoids conflicts but needs a comparison of every tag, so it is costly.
  6. Set-associative mapping places a block in any line of one set, set = $j \bmod S$, and is the usual compromise; the address is divided into tag, index (set) and word (offset) fields.
  7. When the cache is full a replacement algorithm chooses the victim: LRU (least recently used), FIFO or random; direct mapping needs none.
  8. Write-through updates cache and memory together, while write-back updates memory only when the dirty block is replaced.
  9. Cache performance improves with a larger cache, larger block size (up to a point), higher associativity, multilevel caches (L1, L2, L3) and prefetching.

Example. With 8 cache lines, main memory block 13 goes to line $13 \bmod 8 = 5$, and block 21 also goes to line 5, so they conflict. With $h = 0.9$, $T_c = 20$ ns and $T_m = 100$ ns, $T_{avg} = 0.9\times 20 + 0.1\times 100 =$ 28 ns.

Answer frame. Open with the definition; draw the hierarchy figure; develop hit and miss, the average time formula, the three mapping schemes, replacement and write policy; close with the ways to improve performance.

Virtual Memory

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Definition. <mark>Virtual memory is a technique that lets a program use a logical address space larger than physical memory by keeping the unused parts on disk and bringing them in on demand.</mark>

Key points.

  1. The programmer sees one large logical (virtual) address space, and hardware with the operating system maps it to the smaller physical space.
  2. In paging, the logical space is divided into equal fixed-size pages and physical memory into frames of the same size.
  3. A page table stores the frame number for each page number, together with a valid bit and a dirty bit.
  4. A page fault occurs when the required page is not in memory; the operating system loads it from disk and restarts the instruction.
  5. In segmentation, a program is divided into variable-size logical units such as code, data and stack; each segment has a base and a limit in a segment table.
  6. Paging has no external fragmentation but has internal fragmentation, while segmentation follows the user's view but suffers external fragmentation.
  7. Page replacement policies are FIFO, LRU and optimal; a poor choice causes thrashing.
Point Paging Segmentation
Unit size Fixed Variable
View Invisible to the user Matches program structure
Fragmentation Internal External
Table Page table Segment table (base, limit)

Example. A 32-bit logical address with 4 KB pages has 12 offset bits and 20 page-number bits, so the page table has $2^{20}$ entries.

Answer frame. Open with the definition; give the paging idea with a page table figure; develop page fault and replacement; add the paging versus segmentation table; close with the benefit of running large programs.

memory management hardware

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Definition. <mark>The memory management unit (MMU) is hardware that translates logical addresses into physical addresses at run time and enforces memory protection.</mark>

Diagram.

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Key points.

  1. The logical address is split into page number and offset; the page number is translated to a frame number and the offset is copied unchanged.
  2. A page table lookup costs an extra memory access, so the MMU keeps a TLB (translation lookaside buffer), a small associative cache of recent translations.
  3. On a TLB hit the frame number is available at once, and on a miss the page table is read and the TLB is updated.
  4. Effective access time is $h(t_{TLB}+t_m) + (1-h)(t_{TLB}+2t_m)$.
  5. Protection bits (valid, read, write, execute) in each entry stop illegal access, and base and limit registers protect segments.

Example. With $h=0.8$, $t_{TLB}=20$ ns and $t_m=100$ ns, the time is $0.8\times120 + 0.2\times220 =$ 140 ns.

Answer frame. Open with the MMU definition; draw the translation figure; develop TLB hit and miss, the formula and protection; close with the speed gain from the TLB.

Last-minute revision

  • RAM is volatile; ROM is non-volatile and holds the boot program.
  • SRAM uses flip-flops and is used for cache; DRAM needs refresh and is used for main memory.
  • ROM types in order: mask ROM, PROM, EPROM (UV erase), EEPROM (electric erase).
  • Disk access time = seek + rotational latency + transfer; latency is half a rotation on average.
  • Tape is sequential; disk and optical media are direct access.
  • Direct mapping: line = block mod number of lines; set-associative: set = block mod number of sets.
  • Hit ratio = hits divided by total accesses.
  • Average access time = $h T_c + (1-h) T_m$.
  • Cache replacement: LRU, FIFO, random; write policies: write-through and write-back.
  • Virtual memory uses pages, frames and a page table; a page fault loads the page from disk.
  • The TLB caches page-table entries; effective time = $h(t_{TLB}+t_m)+(1-h)(t_{TLB}+2t_m)$.

Memory hooks

  • SRAM = Speedy and costly (cache); DRAM = Dies without refresh (main memory).
  • PROM, EPROM, EEPROM: Once, Ultraviolet, Electric.
  • Seek, Spin, Send: the three parts of disk access time.
  • Direct = one place, Associative = any place, Set = any place in a set.
  • Page = fixed size, Segment = varied size.
  • TLB = a cache for the page table.

Coverage checklist

  • Main memory-RAM, ROM: covered; no past questions.
  • Secondary Memory –Magnetic Tape, Disk, Optical Storage: covered; no past questions.
  • Cache Memory: Cache Structure and Design, Mapping Scheme, Replacement Algorithm, Improving Cache Performance: covered; no past questions.
  • Virtual Memory: covered; no past questions.
  • memory management hardware: covered; no past questions.
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