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AD-503 (C) · Computer Org. & Architecture/Quick Revision Short Notes

Computer Org. & Architecture (AD-503 (C)) - Unit 3 Short Notes

How unit 3 is examined

This unit covers I/O buses (PCI, SCSI, USB), modes of data transfer, DMA and the I/O processor; no topic was asked in recent papers, so learn the definitions and the comparisons.

I/O Interface: PCI Bus, SCSI Bus, USB

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Not asked since 2022</span>

Definition. An I/O interface is the hardware between the CPU/memory and a peripheral that converts signals, speed and data format so the two can communicate.

Key points.

  1. PCI (Peripheral Component Interconnect) is a 32/64-bit synchronous parallel bus, clocked at 33 or 66 MHz, that connects fast devices such as graphics and network cards to the processor through a bridge.

  2. PCI supports plug-and-play configuration, so the system assigns addresses and interrupts automatically.

  3. SCSI (Small Computer System Interface) is a parallel bus that daisy-chains up to 8 or 16 devices such as disks and tapes, each with a unique ID and a terminator at the end.

  4. USB (Universal Serial Bus) is a serial, hot-pluggable, plug-and-play bus in which a host controller connects up to 127 devices through hubs in a tree.

  5. USB also supplies power (5 V) to the device; speeds are 1.5 Mbps (low), 12 Mbps (full), 480 Mbps (USB 2.0 high) and 5 Gbps (USB 3.0).

  6. PCI is a shared bus with a bridge: the host bridge joins the CPU-memory bus to the PCI bus, and a second bridge can lead to the slower ISA or expansion bus.

  7. SCSI transfers data asynchronously or synchronously, and a device can disconnect during a slow operation so that another device uses the bus (overlapped I/O).

  8. USB uses a differential pair (D+ and D-) for data plus power and ground wires, and the host polls each device, so no device can start a transfer on its own.

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u3-01" viewBox="0 0 474 252" width="474" height="252" role="img" aria-label="PCI bus layout. Br = host bridge, Gfx = graphics card, Net = network card, SCSI = SCSI host adapter"><style>#dsfig-u3-01 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u3-01 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u3-01 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u3-01 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u3-01 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u3-01 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u3-01 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u3-01 .t{fill:#16181D;font-weight:500}#dsfig-u3-01 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u3-01 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u3-01 .dot{fill:#16181D}#dsfig-u3-01 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u3-01 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u3-01 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u3-01 .ah{fill:#454C5A}#dsfig-u3-01 .ah.hi{fill:#2340B8}#dsfig-u3-01 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u3-01 .wl .t{font-size:12px;font-weight:700}#dsfig-u3-01 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u3-01 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u3-01 .e{stroke:#B1B7C3}html.dark #dsfig-u3-01 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u3-01 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u3-01 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u3-01 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u3-01 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u3-01 .t{fill:#E6E8ED}html.dark #dsfig-u3-01 .t.inv{fill:#0F1115}html.dark #dsfig-u3-01 .kd{stroke:#E6E8ED}html.dark #dsfig-u3-01 .dot{fill:#E6E8ED}html.dark #dsfig-u3-01 .ann{fill:#8FA3FF}html.dark #dsfig-u3-01 .lbl{fill:#858D9C}html.dark #dsfig-u3-01 .ptr{fill:#8FA3FF}html.dark #dsfig-u3-01 .ah{fill:#B1B7C3}html.dark #dsfig-u3-01 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u3-01 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u3-01 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u3-01 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah5" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh5" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,126 L150,126"/><path class="e" d="M169,59 L169,107"/><path class="e" d="M188,126 L279,126"/><path class="e" d="M313.8,115.5 L411.2,50.5"/><path class="e" d="M317,126 L408,126"/><path class="e" d="M313.8,136.5 L405.4,197.6"/><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="169" cy="126" r="18"/><text class="t" x="169" y="126" dy=".35em" text-anchor="middle">Br</text><circle class="n" cx="169" cy="40" r="18"/><text class="t" x="169" y="40" dy=".35em" text-anchor="middle">Mem</text><circle class="n" cx="298" cy="126" r="18"/><text class="t" x="298" y="126" dy=".35em" text-anchor="middle">PCI</text><circle class="n" cx="427" cy="40" r="18"/><text class="t" x="427" y="40" dy=".35em" text-anchor="middle">Gfx</text><circle class="n" cx="427" cy="126" r="18"/><text class="t" x="427" y="126" dy=".35em" text-anchor="middle">Net</text><rect class="n" x="402" y="197" width="50" height="30" rx="15"/><text class="t" x="427" y="212" dy=".35em" text-anchor="middle">SCSI</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">PCI bus layout. Br = host bridge, Gfx = graphics card, Net = network card, SCSI = SCSI host adapter</figcaption></figure>

Point PCI SCSI USB
Type Internal bus Device bus External serial bus
Transfer Parallel, 32/64 bit Parallel, 8/16 bit Serial
Devices Plug-in cards 8 or 16 disks, tapes Up to 127
Hot plug No No Yes
Typical use Graphics, network Disks, tapes, scanners Keyboard, drives, phones

Answer frame. Open with the definition of an I/O interface; draw the PCI block diagram with the bridge; then develop PCI, SCSI and USB one after the other with three points each; close with the comparison table.

<mark>An I/O interface matches the CPU and a peripheral in signal, speed and format; PCI is the internal parallel bus, SCSI the parallel device chain, USB the serial hot-plug bus.</mark>

Data Transfer: Serial, Parallel, Synchronous, Asynchronous

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Not asked since 2022</span>

Definition. Data transfer is the movement of bits between two units; serial sends one bit at a time on one line, parallel sends all bits of a word together on many lines.

Key points.

  1. Serial transfer needs one data line, so it is cheap and suits long distances, but it is slow.
  2. Parallel transfer needs one line per bit, so it is fast over short distances but costly and prone to skew.
  3. In synchronous transfer both units share a common clock, and data moves at clock edges with no extra signalling.
  4. In asynchronous transfer there is no common clock; strobe control (one control line) or handshaking (request and acknowledge lines) coordinates each transfer.
  5. Handshaking is more reliable than a strobe because the receiver confirms it has accepted the data.
Point Synchronous Asynchronous
Clock Common clock No common clock
Control Clock edges Strobe or handshake
Speed Faster Slower
  1. In strobe control initiated by the source, the source places data on the bus and then pulses the strobe; the destination latches data on the strobe edge, but the source cannot know that the data was received.
  2. In strobe control initiated by the destination, the destination pulses the strobe first and the source then supplies data, but the destination cannot know that the source really placed valid data.
  3. Source-initiated handshake: the source puts data on the bus and raises Data Valid; the destination accepts the data and raises Data Accepted; the source drops Data Valid; the destination drops Data Accepted. Both units are therefore certain that the transfer took place.

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u3-02" viewBox="0 0 338 80" width="338" height="80" role="img" aria-label="Source-initiated handshake between the source and the destination units. Data travels on the data bus alongside these two control lines"><style>#dsfig-u3-02 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u3-02 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u3-02 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u3-02 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u3-02 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u3-02 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u3-02 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u3-02 .t{fill:#16181D;font-weight:500}#dsfig-u3-02 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u3-02 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u3-02 .dot{fill:#16181D}#dsfig-u3-02 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u3-02 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u3-02 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u3-02 .ah{fill:#454C5A}#dsfig-u3-02 .ah.hi{fill:#2340B8}#dsfig-u3-02 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u3-02 .wl .t{font-size:12px;font-weight:700}#dsfig-u3-02 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u3-02 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u3-02 .e{stroke:#B1B7C3}html.dark #dsfig-u3-02 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u3-02 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u3-02 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u3-02 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u3-02 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u3-02 .t{fill:#E6E8ED}html.dark #dsfig-u3-02 .t.inv{fill:#0F1115}html.dark #dsfig-u3-02 .kd{stroke:#E6E8ED}html.dark #dsfig-u3-02 .dot{fill:#E6E8ED}html.dark #dsfig-u3-02 .ann{fill:#8FA3FF}html.dark #dsfig-u3-02 .lbl{fill:#858D9C}html.dark #dsfig-u3-02 .ptr{fill:#8FA3FF}html.dark #dsfig-u3-02 .ah{fill:#B1B7C3}html.dark #dsfig-u3-02 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u3-02 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u3-02 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u3-02 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah6" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh6" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M58.4,44.6 Q169,72 277.6,45.1" marker-end="url(#ah6)"/><path class="e" d="M279.6,35.4 Q169,8 60.4,34.9" marker-end="url(#ah6)"/><g class="wl"><rect x="130.6" y="49.4" width="75.9" height="18" rx="9"/><text class="t" x="168.5" y="58.4" dy=".35em" text-anchor="middle">DataValid</text></g><g class="wl"><rect x="135.1" y="12.6" width="68.7" height="18" rx="9"/><text class="t" x="169.5" y="21.6" dy=".35em" text-anchor="middle">Accepted</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Src</text><circle class="n" cx="298" cy="40" r="18"/><text class="t" x="298" y="40" dy=".35em" text-anchor="middle">Dst</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Source-initiated handshake between the source and the destination units. Data travels on the data bus alongside these two control lines</figcaption></figure>

Steps.

Step 1: Source places data on the bus and enables Data Valid.
Step 2: Destination latches the data and enables Data Accepted.
Step 3: Source disables Data Valid and removes the data.
Step 4: Destination disables Data Accepted; the bus is ready for the next word.

Serial modes. Asynchronous serial sends each character with a start bit (0), 5-8 data bits, an optional parity bit and 1-2 stop bits, so the receiver resynchronises on every character. Synchronous serial sends a long block of characters with sync characters at the start and no gap bits, so it has less overhead and is faster.

Example. A character of 8 data bits with 1 start bit and 1 stop bit needs 10 bits on the line, so at 9600 baud the rate is 9600/10 = 960 characters per second.

Answer frame. Open with the definition of serial, parallel, synchronous and asynchronous transfer; draw the handshake diagram; then develop serial versus parallel, then strobe and handshake; close with the sync versus async table.

<mark>Synchronous transfer is timed by a common clock; asynchronous transfer is timed by strobe or handshake signals.</mark>

Direct Memory Access (DMA)

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Not asked since 2022</span>

Definition. DMA is a technique in which a DMA controller transfers a block of data directly between an I/O device and main memory without the CPU handling each word.

Key points.

  1. The CPU initialises the DMA controller with the memory start address, the word count and the direction (read or write), then continues other work.

  2. The controller sends a bus request (HOLD); the CPU finishes its cycle and replies with a bus grant (HLDA), giving up the bus.

  3. In burst mode the controller keeps the bus until the whole block is moved; in cycle stealing it takes the bus for one word at a time between CPU cycles.

  4. When the word count reaches zero the controller interrupts the CPU to report completion.

  5. DMA is faster than interrupt-driven or programmed I/O for bulk data such as disk blocks.

  6. The DMA controller has an address register, a word count register and a control register, and it drives the address bus and the read/write lines while it holds the bus.

  7. Because the controller and the CPU both need the bus, the bus arbitration gives the DMA request priority over the CPU, which only stalls if it needs the bus at that moment.

  8. Unlike interrupt-driven I/O, there is no register save and restore for every word, so the CPU overhead is only at the start and the end of the block.

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u3-03" viewBox="0 0 424 252" width="424" height="252" role="img" aria-label="DMA block diagram. DREQ = device request, DACK = acknowledge, HOLD = bus request, HLDA = bus grant"><style>#dsfig-u3-03 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u3-03 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u3-03 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u3-03 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u3-03 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u3-03 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u3-03 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u3-03 .t{fill:#16181D;font-weight:500}#dsfig-u3-03 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u3-03 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u3-03 .dot{fill:#16181D}#dsfig-u3-03 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u3-03 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u3-03 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u3-03 .ah{fill:#454C5A}#dsfig-u3-03 .ah.hi{fill:#2340B8}#dsfig-u3-03 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u3-03 .wl .t{font-size:12px;font-weight:700}#dsfig-u3-03 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u3-03 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u3-03 .e{stroke:#B1B7C3}html.dark #dsfig-u3-03 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u3-03 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u3-03 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u3-03 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u3-03 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u3-03 .t{fill:#E6E8ED}html.dark #dsfig-u3-03 .t.inv{fill:#0F1115}html.dark #dsfig-u3-03 .kd{stroke:#E6E8ED}html.dark #dsfig-u3-03 .dot{fill:#E6E8ED}html.dark #dsfig-u3-03 .ann{fill:#8FA3FF}html.dark #dsfig-u3-03 .lbl{fill:#858D9C}html.dark #dsfig-u3-03 .ptr{fill:#8FA3FF}html.dark #dsfig-u3-03 .ah{fill:#B1B7C3}html.dark #dsfig-u3-03 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u3-03 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u3-03 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u3-03 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah7" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh7" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M61,40 L191,40" marker-end="url(#ah7)" marker-start="url(#ah7)"/><path class="e" d="M233,40 L363,40" marker-end="url(#ah7)" marker-start="url(#ah7)"/><path class="e" d="M212,61 L212,191" marker-end="url(#ah7)" marker-start="url(#ah7)"/><path class="e" d="M59,40 L365,40"/><g class="wl"><rect x="88.1" y="31" width="75.9" height="18" rx="9"/><text class="t" x="126" y="40" dy=".35em" text-anchor="middle">HOLD/HLDA</text></g><g class="wl"><rect x="260.1" y="31" width="75.9" height="18" rx="9"/><text class="t" x="298" y="40" dy=".35em" text-anchor="middle">addr/data</text></g><g class="wl"><rect x="174.1" y="117" width="75.9" height="18" rx="9"/><text class="t" x="212" y="126" dy=".35em" text-anchor="middle">DREQ/DACK</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">DMA</text><circle class="n" cx="384" cy="40" r="18"/><text class="t" x="384" y="40" dy=".35em" text-anchor="middle">Mem</text><circle class="n" cx="212" cy="212" r="18"/><text class="t" x="212" y="212" dy=".35em" text-anchor="middle">IO</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">DMA block diagram. DREQ = device request, DACK = acknowledge, HOLD = bus request, HLDA = bus grant</figcaption></figure>

Steps.

Step 1: CPU loads address, word count and direction into the DMA controller.
Step 2: Device raises DREQ; controller raises HOLD.
Step 3: CPU completes the current cycle, floats the bus and raises HLDA.
Step 4: Controller sends DACK and transfers a word; address++ and count--.
Step 5: Repeat until count = 0.
Step 6: Controller releases the bus and interrupts the CPU.
Point Burst mode Cycle stealing
Bus use Whole block at once One word at a time
CPU Blocked for the block Slowed slightly
Best for Fast devices Slow devices

Example. A block of 1000 words is moved with 1 microsecond per bus cycle. Burst mode holds the bus for 1000 x 1 = 1000 microseconds continuously; cycle stealing takes the same 1000 cycles but spread between CPU cycles, so the CPU is never blocked for long.

Answer frame. Open with the definition of DMA; draw the block diagram; then develop the steps in order and the two modes; close with the advantage over programmed and interrupt-driven I/O.

<mark>DMA moves a block between device and memory without the CPU, which only starts it and is interrupted at the end.</mark>

I/O Processor

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Not asked since 2022</span>

Definition. An I/O processor (IOP, or channel) is a separate processor with its own instructions that controls I/O transfers, freeing the CPU from I/O supervision.

Key points.

  1. The CPU only starts an I/O program in memory; the IOP fetches and executes the channel commands by itself.

  2. An IOP can handle many devices and do format conversion, error checking and code translation, which a DMA controller cannot.

  3. The IOP shares memory with the CPU and interrupts it only when the whole I/O program finishes.

  4. A selector channel serves one high-speed device at a time; a multiplexer channel serves many slow devices together.

  5. The IOP reads its commands (Command Word, Channel Command Word) from memory; each command has an operation, memory address, count and flags such as end of chain.

  6. Communication is by a message: the CPU tests the IOP status, sends the start-I/O instruction, the IOP fetches the I/O program, and it sends an interrupt when the transfer ends or an error occurs.

  7. The IOP has more capability than DMA: DMA only copies words between device and memory, while the IOP executes a program of many transfers with its own decisions.

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Point DMA I/O Processor
Instruction set None Own instructions
Devices One transfer at a time Many devices
CPU load Low Lowest
Extra work None Error check, code conversion

Answer frame. Open with the definition of the IOP; draw the CPU-memory-IOP-devices diagram; then develop the working steps and the channel types; close with the DMA versus IOP table.

<mark>The IOP is a programmable processor dedicated to I/O, so the CPU only starts the job and takes the completion interrupt.</mark>

Last-minute revision

  • PCI: 32/64-bit synchronous parallel bus, plug-and-play.
  • SCSI: parallel bus, daisy chain of 8 or 16 devices, terminator at the end.
  • USB: serial, hot-pluggable, up to 127 devices, supplies 5 V power.
  • Serial: one line, cheap, slow; parallel: many lines, fast, short distance.
  • Synchronous uses a common clock; asynchronous uses strobe or handshake.
  • Handshake lines: request and acknowledge.
  • DMA control signals: HOLD/HLDA (bus request and grant).
  • Burst mode holds the bus for the whole block; cycle stealing takes one word at a time.
  • The DMA controller holds address, word count and control registers.
  • IOP has its own instruction set; DMA does not.

Memory hooks

  • PCI = Peripheral inside the box; SCSI = Storage chain; USB = Universal plug-in.
  • Strobe = one shout; handshake = shout and reply.
  • Burst = binge; cycle stealing = sip.
  • DMA is a courier; IOP is a manager.

Coverage checklist

  • I/O Interface –PCI Bus, SCSI Bus, USB: definition, PCI, SCSI, USB (no past questions).
  • Data Transfer: Serial, Parallel, Synchronous, Asynchronous Modes of Data Transfer: serial vs parallel, sync vs async table (no past questions).
  • Direct Memory Access(DMA): steps, burst, cycle stealing (no past questions).
  • I/O Processor: role, channels (no past questions).
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