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AD-503 (C) · Computer Org. & Architecture/Quick Revision Short Notes

Computer Org. & Architecture (AD-503 (C)) - Unit 1 Short Notes

How unit 1 is examined

This unit covers the desktop computer, the CPU (registers, control word, stack, instruction formats, ALU, buses), register transfer language with addressing modes, and the control unit (hardwired and microprogrammed); no recent paper questions are tagged, so every topic is taught in short form.

Structure of Desktop Computers

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Definition. <mark>A desktop computer is a stored-program machine in which a CPU, main memory and input/output devices are joined by a system bus, and the CPU executes instructions kept in memory.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-01" viewBox="0 0 252 252" width="252" height="252" role="img" aria-label="Desktop computer - CPU, main memory and I/O devices on the system bus"><style>#dsfig-u1-01 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-01 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-01 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-01 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-01 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-01 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-01 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-01 .t{fill:#16181D;font-weight:500}#dsfig-u1-01 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-01 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-01 .dot{fill:#16181D}#dsfig-u1-01 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-01 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-01 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-01 .ah{fill:#454C5A}#dsfig-u1-01 .ah.hi{fill:#2340B8}#dsfig-u1-01 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-01 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-01 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-01 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-01 .e{stroke:#B1B7C3}html.dark #dsfig-u1-01 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-01 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-01 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-01 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-01 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-01 .t{fill:#E6E8ED}html.dark #dsfig-u1-01 .t.inv{fill:#0F1115}html.dark #dsfig-u1-01 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-01 .dot{fill:#E6E8ED}html.dark #dsfig-u1-01 .ann{fill:#8FA3FF}html.dark #dsfig-u1-01 .lbl{fill:#858D9C}html.dark #dsfig-u1-01 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-01 .ah{fill:#B1B7C3}html.dark #dsfig-u1-01 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-01 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-01 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-01 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah1" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh1" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,126 L107,126"/><path class="e" d="M139.4,112.6 L198.6,53.4"/><path class="e" d="M139.4,139.4 L198.6,198.6"/><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">CPU</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">Mem</text><circle class="n" cx="212" cy="212" r="18"/><text class="t" x="212" y="212" dy=".35em" text-anchor="middle">IO</text><circle class="n" cx="126" cy="126" r="18"/><text class="t" x="126" y="126" dy=".35em" text-anchor="middle">Bus</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Desktop computer - CPU, main memory and I/O devices on the system bus</figcaption></figure>

Key points.

  1. The CPU fetches, decodes and executes instructions, and contains the ALU, the control unit and the registers.
  2. Main memory (RAM) holds the programs and data currently in use and is volatile, while secondary storage such as the hard disk or SSD keeps them permanently.
  3. Input devices (keyboard, mouse) and output devices (monitor, printer) connect through I/O interfaces, which convert device speed and format to the bus.
  4. The motherboard carries the CPU socket, memory slots, chipset and expansion slots, and the buses on it carry data, address and control signals.
  5. The stored-program concept means instructions and data share the same memory, so a program is changed by changing memory contents, not wiring.

CPU: General Register Organization, Stack Organization, Instruction Format, ALU, I/O System, Bus Structure

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Definition. <mark>The CPU is the processing unit that fetches, decodes and executes instructions using its registers, ALU and control unit.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-02" viewBox="0 0 467 252" width="467" height="252" role="img" aria-label="General register organization - registers feed the ALU through two multiplexers (MA, MB) on the bus; the ALU result returns to a register"><style>#dsfig-u1-02 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-02 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-02 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-02 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-02 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-02 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-02 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-02 .t{fill:#16181D;font-weight:500}#dsfig-u1-02 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-02 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-02 .dot{fill:#16181D}#dsfig-u1-02 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-02 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-02 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-02 .ah{fill:#454C5A}#dsfig-u1-02 .ah.hi{fill:#2340B8}#dsfig-u1-02 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-02 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-02 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-02 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-02 .e{stroke:#B1B7C3}html.dark #dsfig-u1-02 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-02 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-02 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-02 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-02 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-02 .t{fill:#E6E8ED}html.dark #dsfig-u1-02 .t.inv{fill:#0F1115}html.dark #dsfig-u1-02 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-02 .dot{fill:#E6E8ED}html.dark #dsfig-u1-02 .ann{fill:#8FA3FF}html.dark #dsfig-u1-02 .lbl{fill:#858D9C}html.dark #dsfig-u1-02 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-02 .ah{fill:#B1B7C3}html.dark #dsfig-u1-02 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-02 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-02 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-02 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah2" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh2" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M55.8,50.5 L153.2,115.5"/><path class="e" d="M59,126 L150,126"/><path class="e" d="M55.8,201.5 L153.2,136.5"/><path class="e" d="M184.8,115.5 L280.5,51.6" marker-end="url(#ah2)"/><path class="e" d="M184.8,136.5 L280.5,200.4" marker-end="url(#ah2)"/><path class="e" d="M313.8,50.5 L409.5,114.4" marker-end="url(#ah2)"/><path class="e" d="M313.8,201.5 L409.5,137.6" marker-end="url(#ah2)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">R1</text><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">R2</text><circle class="n" cx="40" cy="212" r="18"/><text class="t" x="40" y="212" dy=".35em" text-anchor="middle">R3</text><circle class="n" cx="169" cy="126" r="18"/><text class="t" x="169" y="126" dy=".35em" text-anchor="middle">Bus</text><circle class="n" cx="298" cy="40" r="18"/><text class="t" x="298" y="40" dy=".35em" text-anchor="middle">MA</text><circle class="n" cx="298" cy="212" r="18"/><text class="t" x="298" y="212" dy=".35em" text-anchor="middle">MB</text><circle class="n" cx="427" cy="126" r="18"/><text class="t" x="427" y="126" dy=".35em" text-anchor="middle">ALU</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">General register organization - registers feed the ALU through two multiplexers (MA, MB) on the bus; the ALU result returns to a register</figcaption></figure>

Key points.

  1. The Program Counter (PC) holds the address of the next instruction and is incremented after each fetch; the Instruction Register (IR) holds the instruction being executed.
  2. The Memory Address Register (MAR) holds the address to be accessed in memory and the Memory Data Register (MDR) holds the word being read or written.
  3. In general register organization a small set of registers is connected to the ALU through two multiplexers, so a micro-operation such as $R1 \leftarrow R2 + R3$ finishes in one clock.
  4. The control word selects the operation: it has fields for source A (SELA), source B (SELB), destination (SELD) and ALU operation (OPR); with 3 bits for each register field and 5 bits for OPR it is 14 bits long.
  5. A stack is a last-in first-out memory area addressed by the stack pointer (SP): PUSH writes at the top and updates SP, POP reads the top and updates SP in the opposite direction.
  6. Instruction formats are classified by the number of address fields: three-address ($ADD\ R1, R2, R3$), two-address, one-address (accumulator based) and zero-address (stack based, uses PUSH and POP), and each format has an opcode, a mode field and operand fields.
  7. The ALU performs arithmetic (add, subtract) and logic (AND, OR, NOT, shift) operations, and the I/O system connects peripherals to the CPU through interface units.
  8. The bus structure has three sets of lines: the address bus (one way, CPU to memory), the data bus (two way) and the control bus (read, write, interrupt signals).
Format Example Operands in instruction
Three-address ADD R1, A, B 3
Two-address ADD A, B 2
One-address ADD A 1 (other in AC)
Zero-address ADD 0 (top of stack)

Register Transfer Language-Bus and Memory Transfer, addressing modes

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Definition. <mark>Register Transfer Language (RTL) is a symbolic notation that describes data movement between registers, and addressing modes are the rules for finding an operand from the address field of an instruction.</mark>

Key points.

  1. A simple transfer is written $R2 \leftarrow R1$, and a conditional transfer $P: R2 \leftarrow R1$ happens only when the control condition $P$ is true.
  2. Bus transfer uses a common bus with multiplexers (or three-state buffers), so any register can be selected as the source, for example $BUS \leftarrow R1$, $R2 \leftarrow BUS$.
  3. Memory read is written $DR \leftarrow M[AR]$ and memory write is $M[AR] \leftarrow R1$.
  4. Immediate mode has the operand inside the instruction, direct mode gives the operand address, and indirect mode gives the address of the address.
  5. Register mode names a register holding the operand, and register indirect mode names a register holding the operand address.
  6. Indexed mode adds an index register to the address field, $EA = A + (XR)$, and relative mode adds the offset to the program counter, $EA = A + (PC)$.

Control Unit Organization: Basic Concept of Instruction, Instruction Types, Micro Instruction Formats, Fetch and Execution cycle, Hardwired control unit, Microprogrammed Control unit microprogram sequencer Control Memory, Sequencing and Execution of Micro Instruction

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Definition. <mark>The control unit generates the timed control signals that direct the fetch, decode and execute of every instruction.</mark>

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u1-03" viewBox="0 0 467 80" width="467" height="80" role="img" aria-label="Microprogrammed control - sequencer sets the control address register (CAR); control memory (CM) gives the microinstruction in the control data register (CDR)"><style>#dsfig-u1-03 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u1-03 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u1-03 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u1-03 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u1-03 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u1-03 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u1-03 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u1-03 .t{fill:#16181D;font-weight:500}#dsfig-u1-03 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u1-03 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u1-03 .dot{fill:#16181D}#dsfig-u1-03 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u1-03 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u1-03 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u1-03 .ah{fill:#454C5A}#dsfig-u1-03 .ah.hi{fill:#2340B8}#dsfig-u1-03 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u1-03 .wl .t{font-size:12px;font-weight:700}#dsfig-u1-03 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u1-03 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u1-03 .e{stroke:#B1B7C3}html.dark #dsfig-u1-03 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u1-03 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u1-03 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u1-03 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u1-03 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u1-03 .t{fill:#E6E8ED}html.dark #dsfig-u1-03 .t.inv{fill:#0F1115}html.dark #dsfig-u1-03 .kd{stroke:#E6E8ED}html.dark #dsfig-u1-03 .dot{fill:#E6E8ED}html.dark #dsfig-u1-03 .ann{fill:#8FA3FF}html.dark #dsfig-u1-03 .lbl{fill:#858D9C}html.dark #dsfig-u1-03 .ptr{fill:#8FA3FF}html.dark #dsfig-u1-03 .ah{fill:#B1B7C3}html.dark #dsfig-u1-03 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u1-03 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u1-03 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u1-03 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah3" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh3" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L148,40" marker-end="url(#ah3)"/><path class="e" d="M188,40 L277,40" marker-end="url(#ah3)"/><path class="e" d="M317,40 L406,40" marker-end="url(#ah3)"/><path class="e" d="M408,40 L61,40" marker-end="url(#ah3)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">Seq</text><circle class="n" cx="169" cy="40" r="18"/><text class="t" x="169" y="40" dy=".35em" text-anchor="middle">CAR</text><circle class="n" cx="298" cy="40" r="18"/><text class="t" x="298" y="40" dy=".35em" text-anchor="middle">CM</text><circle class="n" cx="427" cy="40" r="18"/><text class="t" x="427" y="40" dy=".35em" text-anchor="middle">CDR</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Microprogrammed control - sequencer sets the control address register (CAR); control memory (CM) gives the microinstruction in the control data register (CDR)</figcaption></figure>

Key points.

  1. An instruction has an opcode that tells the operation and operand fields; instruction types are data transfer, arithmetic and logic, and program control (branch, call).
  2. Fetch cycle: $MAR \leftarrow PC$, $MDR \leftarrow M[MAR]$, $IR \leftarrow MDR$, $PC \leftarrow PC+1$; then decode, fetch the operand if required, and execute.
  3. A hardwired control unit builds control signals with gates, decoders and a counter; it is fast but hard to change.
  4. A microprogrammed control unit stores microinstructions in control memory; it is flexible and easy to modify but slower.
  5. A microinstruction format has fields for the micro-operation, condition select, branch type and next-address (branch address), and a group of microinstructions forms a microprogram, one per machine instruction.
  6. The microprogram sequencer chooses the next control-memory address: increment CAR, branch (conditional or unconditional), call or return through a subroutine register, or map the opcode to a start address.
  7. To execute, the opcode is mapped to the control-memory address of its routine, microinstructions are read in sequence and their control fields drive the datapath.
Hardwired Microprogrammed
Gates and counters Control memory
Fast Slower
Hard to modify Easy to modify
Used in RISC Used in CISC

Last-minute revision

  • A stored program means instructions and data share the same memory.
  • PC holds the next instruction address; IR holds the current instruction.
  • Fetch: $IR \leftarrow M[PC]$, then $PC \leftarrow PC+1$.
  • Instruction formats: three, two, one and zero address.
  • A stack is last-in first-out and is addressed by SP.
  • Control word fields are SELA, SELB, SELD and OPR.
  • Memory read is $DR \leftarrow M[AR]$; write is $M[AR] \leftarrow R1$.
  • Indexed mode: $EA = A + (XR)$; relative: $EA = A + (PC)$.
  • Hardwired control is fast; microprogrammed control is flexible.
  • Control memory stores the microprogram.

Memory hooks

  • Fetch, Decode, Execute: FDE.
  • Hardwired equals hardware speed; micro equals memory flexibility.
  • Zero-address equals stack.
  • Address bus one-way, data bus two-way.

Coverage checklist

  • Structure of Desktop Computers: no past questions.
  • CPU: General Register Organization-Memory Register, Instruction Register, Control Word, Stack Organization, Instruction Format, ALU, I/O System, bus, CPU and Memory Program Counter, Bus Structure: no past questions.
  • Register Transfer Language-Bus and Memory Transfer, addressing modes: no past questions.
  • Control Unit Organization: Basic Concept of Instruction, Instruction Types, Micro Instruction Formats, Fetch and Execution cycle, Hardwired control unit, Microprogrammed Control unit microprogram sequencer Control Memory, Sequencing and Execution of Micro Instruction: no past questions.
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