Microprocessor and Interfacing (IT-503 (B)) - Unit 2 Short Notes

UNIT 2: Microprocessor Architecture & Interfacing (8085/8086 Focus)

Based on Standard RGPV Syllabus Pattern for IT-503(B).
Note: Actual exam questions for this specific course code were not provided in the context. These notes follow the generalized UNIT 2 outline and cover high-frequency topics from past Microprocessor & Interfacing exams.

2.1 Microprocessor Architecture & Basic Concepts Review

2.1.1 Functional Block Diagram

A microprocessor integrates key components onto a single IC:

• ALU (Arithmetic Logic Unit): Performs arithmetic (+,-) and logical (AND, OR, NOT) operations.

• Register Array: Small, fast storage locations (ACC, B, C, D, E, H, L, PC, SP).

• Control Unit (CU): Generates control signals (RD, WR, ALE) to coordinate operations. Decodes instructions.

• Instruction Decoder: Part of CU; interprets opcode.

• Address Buffer/Data Buffer: Drive address/data buses.

• Interrupt Control: Manages interrupt requests.

Exam Tip: Be able to label a blank block diagram of 8085/8086.

2.1.2 8085 Pin Configuration & Signals

• Power Supply: Vcc (+5V), Vss (GND).

• Clock: X1, X2 (crystal), CLK (output).

• Address Bus: 16-bit (A15-A0), multiplexed with data bus in 8085 (AD7-AD0). ALE (Address Latch Enable) demultiplexes.

• Data Bus: 8-bit (D7-D0).

• Control & Status Signals:

  • RD (Read), WR (Write) – active low.

  • IO/M – distinguishes I/O (1) from Memory (0) operation.

  • S0, S1 – status signals for machine cycle identification.

  • READY – inserts wait states if 0.

  • HOLD/HLDA – for DMA.

• Interrupt Signals: INTR, INTA (maskable), RST 7.5, 6.5, 5.5 (restart), TRAP (non-maskable).

2.1.3 Registers Organization (8085)

2.1.4 Memory Organization & Addressing Modes

• Address Space: 8085 has 16-bit address bus → $$\displaystyle 2^{16} = 64 $$ KB memory space (0000H to FFFFH).

• Memory Map: Physical allocation of ROM/RAM within this space.

• Addressing Modes (8085):

  1. Immediate: Operand in instruction (MVI A, 45H).

  2. Register: Operand in register (ADD B).

  3. Direct: 16-bit address in instruction (LDA 2000H).

  4. Register Indirect: Address in register pair (MOV A, M where M = content of HL).

  5. Implicit: No operand (CMA, STC).

2.1.5 Instruction Fetch & Execute Cycle (T-States)

• Machine Cycle: Basic operation (Opcode fetch, memory read/write, I/O read/write).

• T-State: One clock period. Timing diagrams define signal states per T-state.

• Fetch Cycle Example (8085):

  1. T1: PC placed on address bus, ALE goes high.

  2. T2: RD goes low, opcode read from memory.

  3. T3: Opcode placed on data bus, loaded into instruction register.

  4. T4: RD goes high, decode & execute begins.

2.2 Assembly Language Programming

2.2.1 Instruction Set Overview

2.2.2 Addressing Modes (8086 - Key Additions)

• Register Indirect: [BX], [SI], [DI], [BP].

• Based/Indexed: [BX+SI], [BX+DI], [BP+SI], [BP+DI].

• Based/Indexed with Displacement: [BX+SI+04H].

2.2.3 Writing Simple ALP: Delay Subroutine Example

; Delay loop for 8085 (approx delay)

MVI B, FFH     ; Load counter

LOOP: DCR B    ; Decrement B

      JNZ LOOP ; Jump if not zero

RET

Common Pitfall: Forgetting to save/restore registers in subroutines if they are used by caller.

2.2.4 Stack Operations

• LIFO structure. PUSH decrements SP, stores data. POP retrieves data, increments SP.

• CALL/RET: CALL pushes PC onto stack, jumps to subroutine. RET pops PC.

• Interrupts: On INTR, processor pushes PC & flags, jumps to ISR via CALL to address from interrupt vector table.

2.3 Memory Interfacing

2.3.1 Memory Devices

• ROM (Read Only Memory): EPROM (UV-erasable), EEPROM (electrically erasable). Non-volatile, stores code/constants.

• RAM (Random Access Memory): SRAM (static), DRAM (dynamic). Volatile, read/write.

2.3.2 Address Decoding & Chip Select (CS) Logic

• Goal: Generate unique CS signal for each memory chip within the 64KB space.

• Method: Use higher-order address lines (A15-A8) with decoders (e.g., 74138 3-to-8 decoder) or logic gates (AND/NAND).

• Example: Two 4KB RAM chips (0000H-0FFFH, 1000H-1FFFH).

  • Chip 1 CS = A15' . A14' . A13' . A12' . A11 . A10 . A9 . A8 (using NAND: A15 A14 A13 A12 inputs).

  • Chip 2 CS = A15' . A14' . A13' . A12' . A11' . A10 . A9 . A8.

2.3.3 Memory Map Design

Address Range   | Device
----------------|-------------------
0000H - 3FFFH   | ROM (16KB)
4000H - 7FFFH   | RAM (16KB)
8000H - 80FFH   | I/O Port (8255)

• Chip Select Equation: Derived from address range boundaries.

2.3.4 Generation of Control Signals

• Memory Read Cycle: IO/M = 0, RD = 0.

• Memory Write Cycle: IO/M = 0, WR = 0.

• I/O Read Cycle: IO/M = 1, RD = 0.

• I/O Write Cycle: IO/M = 1, WR = 0.

2.3.5 Wait States

• If memory is slower than processor, insert WAIT states by holding READY = 0.

• Increases effective access time: $$\displaystyle T_{access} = (n+1) \times T_{clk} $$, where n = number of wait states.

2.4 Input/Output (I/O) Interfacing

2.4.1 I/O vs. Memory-Mapped I/O

2.4.2 Programmable Peripheral Interface (8255/8255A)

• Purpose: General-purpose I/O chip. Provides 24 programmable I/O lines (Ports A, B, C).

• Pin Diagram: D7-D0 (data bus), CS, RD, WR, A0, A1 (port select/control word select), RESET.

• Control Word Format:

  • Mode Definition: A0, A1 select port/control register.

  • Mode Selection: D6, D5 for Port A, D3, D2 for Port B.

    • 00 = Mode 0 (Basic I/O)

    • 01 = Mode 1 (Strobed I/O)

    • 10 = Mode 2 (Bidirectional Bus for Port A only)

  • Port Direction: D4 (Port A), D1 (Port B), D0 (Port C upper/lower).

    • 1 = Input, 0 = Output.

  • Port C Bit Set/Reset: D7 = 1. Used to set/reset individual PC bits (e.g., for handshaking).

2.4.3 Modes of Operation

• Mode 0 (Simple I/O): No handshaking. Ports A, B, C (split) as input/output.

• Mode 1 (Strobed I/O): Uses PC lines for handshaking (STB, IBF, OBF, ACK). Port A/B can be input or output.

• Mode 2 (Bidirectional Bus): Only for Port A. Uses 5 PC lines for handshaking (bidirectional data bus with INTR).

Example Programming: Initialize 8255 for Port A output, Port B input, Port C upper output, lower input in Mode 0.

Control Word: 10000010B = 82H. MOV A, 82H → OUT 83H.

2.4.4 Synchronous vs. Asynchronous Data Transfer

• Synchronous: Data transfer synchronized by a common clock. Fast, used for high-speed devices.

• Asynchronous: Uses handshaking signals (STROBE, ACKNOWLEDGE). Slower, used for devices with variable speeds.

2.4.5 Handshaking & Strobe Control

• Output Handshaking: CPU writes data → OBF (Output Buffer Full) goes high → Device reads data → ACK low → OBF resets.

• Input Handshaking: Device places data → STB (Strobe) pulse → IBF (Input Buffer Full) high → CPU reads data → IBF resets.

2.5 Interrupt Structure

2.5.1 Interrupt Concepts

• Hardware Interrupt: External signal (INTR, TRAP).

• Software Interrupt: RST n instructions (1-byte CALL to fixed vector).

• Vectored: Interrupt address provided by device (TRAP, RST 5.5-7.5). Fixed vector in 8085.

• Non-Vectored: Address supplied by external hardware (INTA cycle).

• Maskable: Can be disabled by DI or by device (RST 5.5-7.5).

• Non-Maskable: Cannot be disabled (TRAP).

2.5.2 8085 Interrupt Structure

• RST 5.5, 6.5, 7.5 have dedicated pins; INTR is general-purpose.

2.5.3 Interrupt Service Routine (ISR)

1. Save Context: Push registers (PSW, B, D, etc.) onto stack.

2. Service Interrupt: Perform required task.

3. Restore Context: Pop registers in reverse order.

4. Return: EI (if needed), RET (or RETI for 8086).

2.5.4 Programmable Interrupt Controller (8259A)

• Need: Manage multiple interrupt sources, prioritize, cascade, provide vector addresses.

• Block Diagram:

  DiagramSEARCH: 8259A block diagram

• Initialization Command Words (ICWs):

  • ICW1: A0=0. Sets edge/level trigger, single/cascade mode, IC4 (need for ICW4).

  • ICW2: A0=1. Sets base interrupt vector address (e.g., 40H → vectors 40H-47H).

  • ICW3: A0=1. Only in cascade mode. Identifies which IR input has slave.

  • ICW4: A0=1. Sets mode (8085/8086), auto/normal EOI, buffer mode.

• Operation Command Words (OCWs):

  • OCW1: Mask register (enable/disable IR lines).

  • OCW2: Rotation priority, EOI command, specific interrupt.

  • OCW3: Read status, poll command, special mask mode.

2.5.5 Interrupt Latency & Response Time

• Latency: Time from interrupt request to start of ISR.

• 8085 Response Sequence:

  1. Complete current instruction.

  2. Send INTA (for INTR) or recognize vector (for RST/TRAP).

  3. For INTR: Read instruction from data bus (usually RST n or CALL).

  4. Push PC, jump to vector address.

• Minimum Response: 6 clock cycles (for INTR with RST instruction) + ISR setup.

2.6 Direct Memory Access (DMA)

2.6.1 Need for DMA

• Problem: High-speed I/O (disk, graphics) would overload CPU if data transferred via programmed I/O.

• Solution: DMA controller takes control of buses, transfers data directly between I/O and memory, freeing CPU.

2.6.2 DMA Controller – 8257/8237

• Architecture: 4 independent channels. Each channel has:

  • DMA Address Register: Holds memory address.

  • DMA Count Register: Holds byte count (auto-decremented).

  • Mode/Status Register: Transfer type (read/write), address increment/decrement, auto-initialize.

• Signals: HRQ (Halt Request to CPU), HLDA (Halt Acknowledge from CPU), DREQ (DMA Request from I/O), DACK (DMA Acknowledge to I/O), MEMR, MEMW, IOR, IOW.

• Transfer Modes:

  1. Demand: Transfer until DREQ low, then pause.

  2. Single: One byte/word per DREQ; CPU regains control between.

  3. Block: Transfer until count = 0 (or DREQ low).

  4. Cascade: Allows multiple DMAs (8257 as slave to another).

2.6.3 DMA Transfer Cycle

1. I/O device asserts DREQ.

2. 8257 requests bus via HRQ.

3. CPU finishes current bus cycle, releases bus, asserts HLDA.

4. 8257 drives address, control signals (MEMR/IOR or MEMW/IOW), transfers one byte/word.

5. Decrements count. If count ≠ 0, repeat. If count = 0, may auto-initialize registers.

6. Releases bus, clears HRQ.

2.7 Case Studies & Advanced Interfacing

2.7.1 Interfacing a Matrix Keyboard (4x4) using 8255

• Connection: Rows to Port A (output), Columns to Port B (input with pull-ups).

• Scanning:

  1. Ground one row (write 0 to that bit of PA, 1s to others).

  2. Read PB. If any column bit is 0, key in that row/column is pressed.

  3. Debounce, identify key, convert to ASCII.

• Code Snippet:

  
  MVI A, 0FEH   ; Ground row 0 (PA0=0)
  
  OUT 00H       ; To 8255 control port (assuming PA at 00H)
  
  IN 01H        ; Read PB
  
  CMA           ; Invert to get active-high
  
  ANI 0FH       ; Mask lower 4 bits (columns)
  
  JNZ KEY_FOUND ; If not zero, key pressed
  
  

2.7.2 Interfacing Seven-Segment Display (Multiplexed)

• Common Cathode/Anode: Segments (a-g, dp) to one port (e.g., PA), digit select to another (e.g., PB).

• Multiplexing: Rapidly cycle through digits (e.g., 1ms each) using software delay. Human eye sees all lit.

• Code: Load segment code for digit 1 to PA, enable digit 1 (PB bit=1), delay, disable, repeat for next digit.

2.7.3 Interfacing ADC (e.g., 0808/0809)

• 0808: 8-bit, 8-channel ADC.

• Signals: IN0-IN7 (analog inputs), START (conversion start pulse), CLK (external), EOC (End of Conversion, goes high), OE (Output Enable), D7-D0 (digital output).

• Interfacing:

  1. Select channel via address lines (A, B, C).

  2. Send START pulse (short WR pulse to ADC).

  3. Wait for EOC = 1 (polling or interrupt).

  4. Enable output (OE = 1), read data from ADC via data bus.

• Control Signals: IOR/IOW from 8085 used to generate START and OE via decoder.

2.7.4 Serial Communication: USART (8251)

• Purpose: Convert parallel data (CPU) to serial (transmit) and vice versa (receive).

• Signals: TxD (Transmit Data), RxD (Receive Data), TxRDY (Transmitter Ready), RxRDY (Receiver Ready), SYNDET (Sync Detect).

• Asynchronous Framing: Start bit (0), 5-8 data bits, optional parity, stop bit(s) (1).

• Programming: Write Mode Instruction (baud rate, char length, parity), then Command (Tx Enable, Rx Enable).

2.8 Modern Interfacing Concepts (Brief)

2.8.1 Bus Standards (Conceptual)

• ISA (AT Bus): 16-bit, 8MHz, legacy.

• PCI: 32/64-bit, shared bus, plug-and-play (configuration space).

• PCIe: High-speed serial, point-to-point, scalable (x1, x4, x16 lanes).

• USB: Serial, hot-plug, host-controlled, up to 127 devices.

2.8.2 Plug-and-Play (PnP)

• System assigns resources (IRQ, DMA, I/O addr, memory) automatically at boot.

• Uses configuration registers in devices (PCI Configuration Space).

2.8.3 Memory-Mapped I/O in Modern Systems

• Dominant method. I/O devices appear as memory locations.

• Example: GPU frame buffer mapped to physical address range.

• Advantages: Full address space, flexible, uses standard load/store instructions.

2.8.4 Advanced Programmable Interrupt Controller (APIC)

• Replaces 8259A in multi-processor systems (x86).

• Local APIC: One per CPU core, handles local interrupts (timer, thermal, inter-processor interrupts - IPI).

• I/O APIC: One per system, collects external interrupts, routes to Local APICs.

• Supports 255 interrupt vectors, dynamic priority, message-signaled interrupts (MSI).

Key Formulas & Constants

• Address Space: $N$ address lines → $$\displaystyle 2^N $$ locations.

• Memory Access Time with Wait States:

$$T_{access} = (n + 1) \times T_{clk}$$

where $n$ = number of wait states.

• 8255 Control Word (Mode 0 Example):

$$\text{Control Word} = \text{D7 D6 D5 D4 D3 D2 D1 D0}$$

D7=1 for bit set/reset mode, else D7=0 for I/O mode.

• DMA Transfer Time (Block Mode):

$$T_{transfer} = \text{Count} \times T_{cycle}$$

$$\displaystyle T_{cycle} $$ includes memory access time + bus grant/return overhead.

Final Exam Strategy:

1. Draw & Label: Practice block diagrams (8085, 8255, 8259A, 8257).

2. Timing: Be able to draw timing diagrams for MEMR, MEMW, IOR, IOW cycles.

3. Programming: Write short ALP for delay, data transfer, interfacing (keyboard scan, 8255 init).

4. Interfacing: Design simple memory maps with decoders. Explain CS logic equations.

5. Compare: I/O vs Memory-mapped, 8255 modes, synchronous vs asynchronous transfer.