Microprocessor and Interfacing (IT-503 (B)) - Unit 1 Short Notes

UNIT 1: Introduction to Microprocessors and 8085 Architecture

1.1 Introduction to Microprocessors

A microprocessor is an integrated circuit that contains the functions of a central processing unit (CPU) of a computer. It is the "brain" that performs arithmetic, logic, control, and input/output operations.

Evolution (by data width):

Basic Components of a Microprocessor:

1. Arithmetic and Logic Unit (ALU): Performs all arithmetic (add, subtract) and logical (AND, OR, XOR) operations.

2. Control Unit (CU): Generates control signals to coordinate operations of ALU, registers, and external devices.

3. Registers: Fast, on-chip memory locations for temporary data storage during execution.

4. System Bus: Pathways for data, address, and control signals (internal & external).

Microprocessor vs. Microcontroller vs. Microcomputer:

Block Diagram of a Typical Microcomputer System:

+----------------+     +----------------+     +----------------+

|    CPU         |     |    Memory      |     |    I/O Devices |
| ( µP + CU )    |<--->| (RAM, ROM)     |<--->| (Keyboard,     |
|                | Bus |                | Bus | Display, etc.) |

+----------------+     +----------------+     +----------------+

        ^                      ^                      ^

        |                      |                      |

        +--------[ System Bus (Address, Data, Control) ]-------+

• System Bus: Set of parallel wires. Subdivided into:

  • Address Bus: Carries memory/I/O addresses (unidirectional from CPU).

  • Data Bus: Carries data and instructions (bidirectional).

  • Control Bus: Carries read/write, clock, interrupt signals.

Historical Context (Intel):

• Intel 4004 (1971): First commercial µP, 4-bit, 2,300 transistors, 740 kHz.

• Intel 8080 (1974): First widely accepted 8-bit µP, 4,500 transistors, 2 MHz.

• Intel 8085 (1977): Improved 8080, single +5V supply, integrated clock generator, 5 MHz.

• Intel 8086/8088 (1978): First 16-bit µP, introduced x86 architecture, segment registers.

[!TIP] Common Pitfall: Do not confuse a microprocessor (CPU only) with a microcontroller (complete system on chip). The 8085 is a classic µP example.

1.2 8085 Microprocessor Architecture

The Intel 8085 is an 8-bit, general-purpose µP. Its architecture is based on a von Neumann model (shared memory for data/instructions).

Detailed Block Diagram & Functional Units:

1. Arithmetic and Logic Unit (ALU): Performs operations on 8-bit data. Results affect flag bits.

2. Control and Timing Unit: Generates all internal and external control signals using a clock (from X1/X2 pins). Manages machine cycles (Fetch, Decode, Execute).

3. General Purpose Registers (6 x 8-bit): B, C, D, E, H, L. Can be used as three 16-bit register pairs: BC, DE, HL. HL is primarily used for memory addressing (as a Memory Address Register - MAR).

4. Special Purpose Registers:

   • Accumulator (A): 8-bit register. Implicit operand for most ALU operations. Primary register for I/O.

   • Program Counter (PC): 16-bit. Holds the address of the next instruction to be fetched.

   • Stack Pointer (SP): 16-bit. Points to the top of the stack in RAM (LIFO structure).

5. Temporary Registers (Internal): W, Z. Used internally by the µP during operations like LDA, STA, SHLD, LHLD to hold the high/low byte of a 16-bit address. Not accessible to the programmer.

6. Flag Register (Status Register): 8-bit register, but only 5 bits are used for flags.

7. Internal Data Bus & Address Bus: 8-bit internal data bus. 16-bit address bus, but the lower 8 bits (A0-A7) are multiplexed with the data bus on pins AD0-AD7.

Register Organization Summary:

Flag Register (Status Register):

[!TIP] Key Point: AC is only affected by lower nibble (bits 0-3). It's crucial for Decimal Adjust Accumulator (DAA) instruction after BCD addition.

ALU Functionality: Performs operations like ADD, SUB, ANA (AND), ORA (OR), XRA (XOR), CMP (Compare), and shifts/rotates (RLC, RRC, RAL, RAR). All operations (except CMP) store result in Accumulator. CMP subtracts but doesn't store result, only updates flags.

Control and Timing Unit:

• Uses a crystal oscillator connected to X1 and X2 pins to generate the basic clock frequency.

• Divides this frequency to produce the system clock (CLK OUT) for peripheral devices.

• Generates all necessary control signals (RD, WR, ALE, IO/M, S0, S1) synchronized with the clock.

Internal Buses:

• Internal Data Bus: 8-bit wide, connects all internal registers to ALU.

• Address Bus: 16-bit wide internally. Externally, A8-A15 are dedicated address lines. AD0-AD7 are multiplexed (carry address in T1, data in T2/T3).

1.3 Pin Configuration and Signal Description of 8085

The 8085 is a 40-pin DIP (Dual In-line Package) IC.

Pin Diagram (Mental Map):

• Top Row (1-20): Power, Clock, Address/Data (Multiplexed), Control, Interrupts, Reset.

• Bottom Row (21-40): Address (High), Data/Address (Multiplexed), Status, Serial I/O, Ground.

Pin Description by Category:

1. Address Bus:

• A8-A15 (Pins 21-28): Unidirectional output. Carry the higher 8 bits of a 16-bit address (for memory/I/O). Not multiplexed.

2. Multiplexed Address/Data Bus:

• AD0-AD7 (Pins 12-19): Bidirectional, multiplexed.

  • During T1 state of a machine cycle: Carry the lower 8 bits of the address (A0-A7).

  • During T2/T3 states: Carry 8-bit data (read/write).

  • Demultiplexing required: Use ALE signal and an external latch (e.g., 74LS373) to separate address from data.

3. Control & Status Signals:

• ALE (Pin 20): Address Latch Enable. A short positive pulse in T1. Used to demultiplex AD0-AD7. When ALE=1, AD bus contains address; when ALE=0, AD bus contains data.

• RD (Pin 21): Read Control. Active low. Indicates µP is reading data from selected memory or I/O device.

• WR (Pin 22): Write Control. Active low. Indicates µP is writing data to selected memory or I/O device.

• IO/M (Pin 23): I/O or Memory. Distinguishes between I/O and memory access.

  • IO/M = 0 → Memory read/write operation.

  • IO/M = 1 → I/O read/write operation.

• S0, S1 (Pins 29, 30): Status signals. Encode the type of machine cycle in progress (Opcode fetch, Memory read/write, I/O read/write, Interrupt Acknowledge).

4. Clock Signals:

• X1, X2 (Pins 1, 2): Crystal oscillator connections. Frequency of crystal is divided by 2 to generate internal clock.

• CLK OUT (Pin 37): System clock output. Provides clock signal to peripheral devices.

5. Interrupt Signals (Priority from High to Low):

• TRAP (Pin 6): Non-maskable, highest priority, edge/level triggered. Used for critical events like power failure.

• RST 7.5, RST 6.5, RST 5.5 (Pins 7, 8, 9): Maskable, vectored interrupts. Have fixed memory addresses (RST n → CALL to n * 8). Can be disabled by DI instruction.

• INTR (Pin 10): General maskable interrupt. Lowest priority. No fixed address; requires external hardware to provide RST or CALL instruction via INTA.

• INTA (Pin 11): Interrupt Acknowledge. µP sends this when it acknowledges INTR.

6. Other Important Signals:

• RESET IN (Pin 36): Active low. Resets µP (PC=0000H, interrupts disabled). Must be held low for at least 3 clock cycles.

• RESET OUT (Pin 3): Active high. Indicates µP is in reset state. Can be used to reset other devices.

• READY (Pin 40): Wait state control. If READY=0, µP enters WAIT state (holds control signals) until READY=1. Used to interface with slow peripherals.

• HOLD (Pin 31) & HLDA (Pin 32): DMA Request/Grant. External device (e.g., disk controller) requests control of system bus via HOLD. µP completes current operation, releases bus, and asserts HLDA.

• SID (Pin 5) & SOD (Pin 4): Serial Input Data / Serial Output Data. Used for simple serial communication (1 bit at a time). Controlled by RIM (Read Interrupt Mask) and SIM (Set Interrupt Mask) instructions.

• VCC (Pin 40) & GND (Pins 20, 11): Power supply (+5V) and ground.

[!TIP] Critical for Exams: Know the function of ALE and the difference between RD/WR and IO/M. Remember IO/M=0 for Memory, IO/M=1 for I/O. Also, know the interrupt priority order: TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR.

1.4 Instruction Set of 8085

Instructions are classified by length (bytes):

• 1-byte: Opcode only (e.g., CMA, RLC). Operand is implied.

• 2-byte: Opcode + 8-bit data/address low byte (e.g., MVI A, 05H, JMP 2000H).

• 3-byte: Opcode + 16-bit address (e.g., LDA 2000H, CALL 3000H).

Classification by Function:

[!TIP] Memory: LDA/STA are 3-byte direct instructions. LDAX/STAX are 1-byte register-indirect (only BC/DE pairs, not HL). MOV M, r and MOV r, M use HL as implied address.

1.5 Addressing Modes of 8085

How an operand (data or address) is specified in an instruction.

[!TIP] Common Confusion: MOV M, r and MOV r, M are register-indirect (using HL). LDAX rp uses BC or DE pairs. LDA addr is direct addressing.

1.6 Assembly Language Programming Basics

Structure of an 8085 Assembly Program:

Label      Mnemonic   Operand     Comment

START:     LXI H, 2050H   ; HL points to first number

           MVI C, 02H     ; Counter = 2

           MOV A, M       ; A = first number

BACK:      INX H          ; HL → next location

           ADD M          ; Add next number to A

           DCR C          ; Decrement counter

           JNZ BACK       ; Loop if C != 0

           STA 2052H      ; Store sum

           HLT            ; Stop

           END START      ; Assembler directive

• Label: Symbolic address for a memory location (e.g., START, BACK). Must start in column 1.

• Mnemonic: Instruction code (e.g., LXI, MOV, ADD).

• Operand: Data or address required by instruction.

• Comment: Begins with ;. For documentation only.

Common Assembler Directives (for assembler, not µP):

• ORG address: Set origin (starting address) for program.

• END [label]: Marks end of source program; optional start label.

• EQU: Equate - assigns a constant value to a label (e.g., N EQU 05H).

• DS n: Define Storage - reserves n bytes of memory (uninitialized).

• DB data_list: Define Byte - stores listed bytes in consecutive memory.

Simple Program Examples:

1. Addition of two 8-bit numbers (memory locations 2050H, 2051H → store sum at 2052H):

   
       LXI H, 2050H   ; HL → first number
   
       MOV A, M       ; A = [2050H]
   
       INX H          ; HL → second number
   
       ADD M          ; A = A + [2051H]
   
       STA 2052H      ; [2052H] = sum
   
       HLT
   
   

2. Find largest number in an array (size N at 2050H, array from 2051H):

   
       LXI H, 2051H   ; HL → first array element
   
       MOV C, M       ; C = N (counter)
   
       INX H          ; HL → second element
   
       MOV A, M       ; A = current max (first element)
   
       DCR C          ; N-1 comparisons left
   
   LOOP:  INX H
   
       CMP M          ; Compare A with next element
   
       JC SKIP        ; If A < [HL], carry=1 → jump (A is smaller)
   
       MOV A, M       ; Else, new max in A
   
   SKIP:  DCR C
   
       JNZ LOOP
   
       STA 2050H      ; Store max at fixed location (overwrite N)
   
       HLT
   
   

Machine Cycles and T-states:

• Machine Cycle (MC): Time required to complete one basic operation (e.g., opcode fetch, memory read). Each MC consists of 3, 4, or 5 T-states.

• T-state: Time of one clock period. Basic timing unit.

• Example: MVI A, 05H (2-byte instruction) takes 2 Machine Cycles:

  • Opcode Fetch (4 T-states): Read opcode from memory.

  • Memory Read (3 T-states): Read operand (05H) from next memory location.

  • Total = 7 T-states.

[!TIP] Programming: For array operations, use HL as pointer, INX H/DCX H to move. Use a register (B/C) as counter. CMP sets flags but doesn't change A. JC/JNC are used after CMP to check if A < operand (Carry=1) or A >= operand (Carry=0).

END OF UNIT 1 NOTES