Computer Architecture (IT-402) - Unit 2 Short Notes

Fixed-Point Number Representations

Fixed-point numbers represent integers and fractions with a fixed number of digits after the binary point. The three primary representations are:

$$-(2^{n-1}-1) \text{ to } +(2^{n-1}-1)$$

| - Simple, human-readable.<br>- Two representations for zero (positive/negative).<br>- Arithmetic logic complex (separate sign/magnitude handling). | | 1's Complement | Negative of a number is obtained by flipping all bits. |

$$-(2^{n-1}-1) \text{ to } +(2^{n-1}-1)$$

| - End-around carry required in addition.<br>- Two representations for zero (all 0s, all 1s).<br>- Simpler hardware than sign-magnitude but still has dual zero. | | 2's Complement | Negative of a number is 1's complement + 1. |

$$-2^{n-1} \text{ to } +(2^{n-1}-1)$$

| - Single representation for zero.<br>- No end-around carry; simpler arithmetic logic.<br>- Most widely used in modern systems. |

[!TIP] Exam Focus:

• Range Calculation: Always remember the asymmetric range in 2's complement ($$\displaystyle -2^{n-1} $$ vs $$\displaystyle 2^{n-1}-1 $$).

• Overflow: Occurs when adding two positives yields negative, or two negatives yields positive.

• Conversion: To convert -X to 2's complement: invert bits of +X and add 1.

Floating-Point Representation and Operations

Based on IEEE 754 standard (single precision: 1 sign bit, 8 exponent bits (bias=127), 23 mantissa bits). A number is represented as:

$$(-1)^S \times (1.M) \times 2^{(E - \text{bias})}$$

where $S$ = sign bit, $M$ = mantissa (fraction), $E$ = stored exponent.

Flowchart for Floating-Point Addition/Subtraction:

1. Align Exponents:

   • Compare exponents $$\displaystyle E_1 $$ and $$\displaystyle E_2 $$.

   • Shift the mantissa of the smaller exponent right until exponents match.

   • Loss of precision may occur if shift is large.

2. Add/Subtract Mantissas:

   • Perform operation on aligned mantissas $$\displaystyle M_1' $$ and $$\displaystyle M_2' $$.

   • Consider sign bits (use 2's complement arithmetic if needed).

3. Normalize Result:

   • If result is $0.xxxx$, shift left and decrement exponent.

   • If result is $10.xxxx$, shift right and increment exponent.

4. Round: Apply rounding (e.g., guard, round, sticky bits).

5. Check for Overflow/Underflow:

   • Overflow: Exponent > max representable.

   • Underflow: Exponent < min representable (or becomes zero).

[!TIP] Common Pitfall:

• Alignment step is critical; forgetting to adjust the exponent of the larger number causes errors.

• Normalization may require multiple shifts; ensure exponent is updated correctly each shift.

Multiplication Algorithms: Booth's Algorithm

Booth's algorithm efficiently multiplies two signed binary numbers by examining consecutive bits of the multiplier to reduce the number of addition/subtraction operations.

Algorithm Steps:

1. Initialize:

   • $[A]$ = 0 (n-bit accumulator).

   • $[Q]$ = multiplier (n bits).

   • $$\displaystyle [Q_{-1}] $$ = 0 (extra bit).

   • $[M]$ = multiplicand (n bits).

   • Count = n.

2. Repeat until count=0:

   • Examine $$\displaystyle Q_0 $$ and $$\displaystyle Q_{-1} $$:

     • 00 or 11 → just arithmetic right shift $$\displaystyle [A, Q, Q_{-1}] $$.

     • 01 → $$\displaystyle [A] = [A] + [M] $$, then shift.

     • 10 → $$\displaystyle [A] = [A] - [M] $$ (add 2's complement of M), then shift.

   • Arithmetic right shift preserves sign.

3. Result: Combined $[A, Q]$ holds product (2n bits).

Example: Multiply $-4 \times 3$ (4-bit representation)

• $-4$ in 2's complement (4-bit): $1100$ ($M$)

• $+3$: $0011$ ($Q$)

Final Product: $$\displaystyle [A,Q] = 11101100 $$ (8-bit 2's complement of $-12$).

Verification: $$\displaystyle -4 \times 3 = -12 $$ ✓.

[!TIP] Why Booth Works:

• It groups runs of 1s in multiplier (e.g., 00111 → 01000 - 00001), reducing additions.

• Key Insight: 10 → subtract M; 01 → add M; 00/11 → no op, just shift.

• Exam Trick: Always extend $[A]$ and $[Q]$ to n+1 bits to handle overflow during addition.