IT-402 Computer Architecture - Jun 2022 Question Paper

Under each question, How to answer lists the points an answer should cover, outlined by CampusPrep from the syllabus. Check the details against your textbook.

1. 7 Marks
   aExplain the Computer architecture and Organization with examples. Also draw the diagram of Van Neumann.
   How to answer

   • Define Computer Architecture with examples (instruction set, data representation, addressing modes).
   • Define Computer Organization with examples (control signals, interfaces, memory technology).
   • Comparison highlighting functional behaviour vs physical realization.
   • Draw Von Neumann architecture block diagram showing CPU (ALU, Control Unit, Registers), Memory, and I/O connected via system buses.
2. 7 Marks
   bWhat is the Register Transfer Language (RTL)? Explain the Arithmetic logic shift unit.
   How to answer

   • Define Register Transfer Language (RTL) and symbolic notation for micro-operations.
   • Explain one stage of an Arithmetic Logic Shift Unit (ALSU).
   • Describe functional block incorporating arithmetic stage (parallel adder/subtractor), logic gates stage, and multiplexer/shifter.
   • Provide function/selection table showing operations based on selection lines (e.g., $S_3, S_2, S_1, S_0, C_{in}$).
3. 7 Marks
   aWhat is the difference between Hardwired and micro programmed control unit?
   How to answer

   • Define Hardwired Control Unit (combinational logic circuits/state machines) and Microprogrammed Control Unit (control store/microinstructions).
   • Tabular comparison based on: Speed, Flexibility, Modification ease, Instruction set complexity, Cost, and Real-world usage (RISC vs CISC).
   • Brief schematic/flow diagram for both control units.
4. 7 Marks
   bExplain the sign-magnitude, 1's and 2's complement. Also define the its range.
   How to answer

   • Define Sign-magnitude form with MSB as sign bit and remaining bits as magnitude; give n-bit range: $-(2^{n-1}-1)$ to $+(2^{n-1}-1)$.
   • Define 1's complement method and its range: $-(2^{n-1}-1)$ to $+(2^{n-1}-1)$ with representations of $\pm 0$.
   • Define 2's complement method (1's complement + 1) and its range: $-2^{n-1}$ to $+(2^{n-1}-1)$.
   • Provide examples of each for a given bit length (e.g., 4 bits or 8 bits).
5. 7 Marks
   aWrite and elaborate note on PCI, SCSI and USB bus standards.
   How to answer

   • Explain PCI (Peripheral Component Interconnect): architecture, synchronous parallel bus, arbitration, bandwidth, and plug-and-play support.
   • Explain SCSI (Small Computer System Interface): device chaining, parallel/serial standards, high-speed storage interfacing.
   • Explain USB (Universal Serial Bus): tiered star topology, packet-based serial communication, plug-and-play, power delivery, and versions.
6. 7 Marks
   bDraw and explain flow charts for additional and subtraction of floating points number.
   How to answer

   • List key phases: zero check, align mantissas (equalizing exponents by shifting smaller mantissa), perform addition or subtraction on mantissas, normalize result, check for overflow/underflow.
   • Draw neat, sequential flowchart for floating-point add/subtract algorithm.
   • Explain each block of the flowchart in step-by-step detail.
7. 14 Marks
   Explain the process of multiplication using BOOTH method. Solve $-4 \times 3$ using Booth method.
   How to answer

   • Explain algorithm rules: examination of bit pairs $(Q_0, Q_{-1})$; $10 \implies A = A - M$, $01 \implies A = A + M$, $00/11 \implies$ shift; Arithmetic Shift Right (ASR).
   • Initialize values using 4-bit (or 5-bit) two's complement: Multiplicand $M = -4 = 1100_2$, $-M = +4 = 0100_2$, Multiplier $Q = 3 = 0011_2$, $A = 0000_2$, $Q_{-1} = 0$, Count $= 4$.
   • Present step-by-step cycle execution in a tabular format showing operations and ASR for each count.
   • Combine final registers $[A, Q]$ to yield $11110100_2 = -12$.
8. 7 Marks
   aExplain the zero, one, two and three address instructions with examples.
   How to answer

   • Define Three-address instruction format with syntax and example evaluating an expression like $X = (A+B) \times (C+D)$.
   • Define Two-address instruction format with syntax and register-transfer example.
   • Define One-address instruction format utilizing an implied Accumulator (AC) register with example.
   • Define Zero-address instruction format utilizing a Stack (PUSH/POP/ADD) with example.
9. 7 Marks
   bDifferentiate between RISC Instructions and CISC instructions with example.
   How to answer

   • Define Reduced Instruction Set Computer (RISC) vs Complex Instruction Set Computer (CISC).
   • Tabulate differences across key parameters: length, execution cycles, registers count, memory access (Load/Store vs Memory-to-memory), control unit implementation.
   • Provide code example comparing multiplication or memory operation in CISC (e.g. MULT A, B) vs RISC (LOAD, LOAD, PROD, STORE).
10. 7 Marks
    aExplain major components of CPU.
    How to answer

    • Identify core components: ALU, Control Unit, Register Set, Internal Bus.
    • Explain function of ALU (arithmetic and logical operations, status flags).
    • Explain function of Control Unit (instruction fetch, decode, timing and control signals).
    • Explain key registers: PC, IR, MAR, MDR, AC, General Purpose Registers.
    • Draw a block diagram of CPU internal structure.
11. 7 Marks
    bThe size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is?
    How to answer

    • Determine maximum transfer capacity of DMA in one burst: 16-bit register can count up to $2^{16} = 65536$ bytes $= 64$ KB (or 65535 bytes).
    • Express file size in KB: $29,154$ KB.
    • Calculate number of DMA transfers: $\lceil 29,154 \text{ KB} / 64 \text{ KB} \rceil = \lceil 455.53125 \rceil = 456$.
    • Conclude that the DMA controller needs to acquire bus control a minimum of 456 times.
12. 7 Marks
    aExplain the hierarchy of Computer memory system with example.
    How to answer

    • Draw the triangular/pyramid memory hierarchy diagram (Registers $\rightarrow$ Cache $\rightarrow$ Main Memory $\rightarrow$ Secondary Storage $\rightarrow$ Tertiary Storage).
    • Explain trade-offs: speed, access time, cost per bit, and storage capacity at each level.
    • Provide typical parameters/examples for each level in a modern computer system.
13. 7 Marks
    bConsider a 2-way set associative mapped cache of size 16KB with block size 256 bytes. The size of main memory is 128 KB. Find the number of bits in the tag directory size.
    How to answer

    • Calculate physical address bits: Main memory $= 128\text{ KB} = 2^{17}\text{ bytes} \implies 17$ address bits.
    • Calculate block offset bits: Block size $= 256\text{ bytes} = 2^8\text{ bytes} \implies 8$ bits.
    • Calculate total lines: $16\text{ KB} / 256\text{ B} = (16 \times 1024) / 256 = 64$ cache lines.
    • Calculate number of sets: $S = 64 / 2 = 32 = 2^5 \implies 5$ set index bits.
    • Calculate tag bits per line: $17 - (5 + 8) = 4$ bits.
    • Calculate total tag directory size: $64 \text{ lines} \times 4 \text{ tag bits} = 256$ bits (or 32 bytes).
14. 14 Marks
    Write short notes on any two of the followings.

    1. i)Virtual memory
    2. ii)Characteristics of Multiprocessors
    3. iii)Instruction Pipeline
    How to answer

    • Virtual Memory: Explain logical vs physical address space, paging/segmentation, page table, and page fault handling.
    • Characteristics of Multiprocessors: Explain shared memory vs distributed memory, MIMD classification, inter-processor communication, cache coherence, and synchronization.
    • Instruction Pipeline: Explain pipelining concept (Fetch, Decode, Execute, Writeback), space-time diagram, speedup calculation, and hazards (data, structural, control).