Electrical CAD Lab (EX-704) - Unit 5 Short Notes

UNIT 5: ADVANCED ELECTRICAL CAD PRACTICES & PROJECT INTEGRATION

5.1 Advanced Schematic & Symbol Management

Focus: Creating reusable, standards-compliant design elements for complex systems.

5.1.1 Creating and Editing Complex, Multi-Part Symbols (IEEE/ANSI)

• Purpose: To represent components with multiple physical units (e.g., dual op-amps, multi-position switches) or variants in a single logical symbol.

• Key Concept: A multi-part symbol contains several "parts" (A, B, C...) within one library component. Each part has its own pin configuration but shares a common component identifier.

• IEEE/ANSI Compliance: Pin numbering and symbol shapes often follow standards (e.g., IEEE 315 for graphic symbols). Use standard pin electrical types (Input, Output, Power, etc.).

• Procedure:

  1. Create a new symbol in the library editor.

  2. Define multiple "parts" within the symbol.

  3. Place pins for each part, ensuring unique pin numbers across all parts.

  4. Set the "Part" count property in the symbol's parameters.

• [!TIP] Exam Focus: Be prepared to draw a simple dual op-amp (e.g., LM358) symbol showing two separate parts (A and B) with correctly assigned pins (1,2,3 for part A; 4,5,6 for part B).

5.1.2 Managing & Customizing Symbol Libraries

• Goal: Organize libraries for team efficiency and design consistency.

• Best Practices:

  • Use a hierarchical folder structure (e.g., Active/Resistors, ICs/Op-Amps, Connectors).

  • Adopt a clear naming convention (e.g., Resistor_ThickFilm_0603, IC_OpAmp_Dual_Generic).

  • Include manufacturer part number and datasheet link in symbol properties.

  • Centralized vs. Local: Use a shared network drive or vault for team libraries; maintain a local cache for speed.

5.1.3 Dynamic Blocks / Parametric Components

• Concept: A single symbol whose graphical representation or properties change based on defined parameters (e.g., a resistor that changes length based on power rating, a switch with variable poles/throws).

• Implementation (Software-dependent):

  • In Altium Designer: Use Parameters and Model links with PCB Model and 3D Model variants.

  • In KiCad/Eagle: Less native support; often managed via multiple symbol variants or external scripts.

• Benefit: Reduces library clutter; one symbol fits multiple part numbers.

5.1.4 Cross-Referencing & Hierarchical Schematic Design

• Hierarchical Design: Breaks a large system into functional blocks (sheets). Each sheet is a separate schematic document.

  • Top Sheet: Contains block symbols representing child sheets.

  • Child Sheets: Contain the detailed circuitry for each block.

• Cross-Referencing: The software automatically generates:

  • Sheet Entry/Port: Connects signals between hierarchical levels.

  • Cross-Reference Report: Lists all sheet entries and their destinations.

• > [!TIP] Common Pitfall: Forgetting to place a Sheet Entry (port) on a child sheet to connect to the top-level net. This creates an ERC error (unconnected net).

5.2 Advanced PCB Layout & Design for Manufacture (DFM)

Focus: Optimizing physical layout for signal integrity, manufacturability, and cost.

5.2.1 Multi-Layer Board Stack-Up Design & Impedance Control

• Stack-Up: The ordered sequence of copper layers and insulating materials (prepreg, core).

  • Typical 4-Layer: Signal 1 (Top), GND Plane (Layer 2), PWR Plane (Layer 3), Signal 2 (Bottom).

• Impedance Control: Calculating trace width/spacing to achieve a target differential or single-ended impedance (usually 50Ω or 100Ω differential).

• Key Formula (Microstrip):

$$ Z_0 = \frac{87}{\sqrt{\varepsilon_r + 1.41}} \ln\left(\frac{5.98h}{0.8w + t}\right) $$

Where:

*   $$\displaystyle Z_0 $$ = Impedance (Ω)

*   $$\displaystyle \varepsilon_r $$ = Dielectric constant of substrate

*   $h$ = Height of trace above reference plane (mils)

*   $w$ = Trace width (mils)

*   $t$ = Trace thickness (mils)

• > [!TIP] Use the PCB manufacturer's stack-up calculator and impedance control tables. Specify impedance requirements in the fabrication drawing.

5.2.2 Advanced Routing Strategies

• Differential Pairs: Route two traces carrying complementary signals.

  • Rules: Keep pairs parallel and equidistant (coupled). Match lengths (tolerance ±5-10mil). Maintain consistent spacing.

  • Tool: Use Interactive Length Tuning with Mitering to minimize discontinuities.

• Length Tuning: Adding "meanders" to match trace lengths for parallel buses (e.g., DDR, LVDS).

• Controlled Impedance Routing: Set specific design rules for target impedance layers; router will adjust width accordingly.

5.2.3 ⭐ Design Rule Checks (DRC) & Electrical Rule Checks (ERC) In-Depth

• DRC (Physical): Checks layout against manufacturing & design constraints.

  • Common Violations:

    | Violation | Cause | Fix | | :--- | :--- | :--- | | Clearance | Trace too close to pad/via | Increase spacing rule or move object | | Short Circuit | Copper from different nets touches | Remove unintended copper, fix polygon pours | | Silkscreen Over Pad | Text on solder joint | Move silkscreen, set design rule |

• ERC (Electrical): Checks schematic connectivity.

  • Common Violations:

    | Violation | Cause | Fix | | :--- | :--- | :--- | | Unconnected Pin (UP) | Pin not connected to net | Connect net or mark as No ERC | | Duplicate Pin | Two pins with same number on same component | Correct pin numbering in symbol | | Power Pin Unconnected | VCC/GND pin not on power net | Connect to correct power port |

• Strategy: Run DRC/ERC iteratively during layout. Fix violations in order of severity (shorts > clearance > warnings).

5.2.4 ⭐ Power Plane Design, Via Types & Thermal Management

• Power Planes: Solid copper areas assigned to a net (e.g., +5V, GND).

  • Benefits: Low impedance, current carrying capacity, EMI shielding.

  • Design: Use Polygon Pour with Pour Over Same Net and Remove Dead Copper.

  • Split Planes: Use for multiple power domains (e.g., analog/digital). Caution: Creates moats; avoid routing signals across splits.

• Via Types:

  • Through-hole: Goes through all layers. Most common, cheapest.

  • Blind: Starts on outer layer, ends on an internal layer.

  • Buried: Connects only internal layers. Most expensive.

• Thermal Management:

  • Use thermal reliefs for component pads on planes (spoke connections) to prevent solder wicking.

  • Add thermal vias under heat-generating components (e.g., regulators, MOSFETs) to connect to internal planes/heat sinks.

  • Use copper pours for heat spreading.

5.2.5 Component Placement Optimization

• Guidelines:

  1. Critical Components First: Place connectors, power supplies, high-speed ICs, and mechanical mounting holes.

  2. Group by Function: Keep analog, digital, power sections physically separated.

  3. Minimize Cross-overs: Reduces layer changes, improves signal integrity.

  4. Thermal: Place heat sinks near board edges; keep hot components away from sensitive ones.

  5. Manufacturing: Orient polarized components (caps, diodes) consistently. Provide adequate spacing for soldering/assembly.

5.3 Integration with Simulation & Analysis Tools

Focus: Linking CAD design to external analysis for verification.

5.3.1 Exporting Netlists for SPICE

• Netlist: A text file listing all components and their interconnections (nets).

• Process: From schematic, export netlist (.net, .cir format). Import into SPICE simulator (e.g., LTspice, PSpice).

• Use Case: Verify analog circuit behavior (op-amp filters, power supplies) before PCB layout.

5.3.2 ⭐ Signal Integrity (SI) & Power Integrity (PI) Analysis Integration

• SI: Analyzes signal quality (ringing, reflections, crosstalk). Requires IBIS models of active components.

• PI: Analyzes power distribution network (PDN) impedance, voltage droop, ground bounce.

• CAD Integration:

  1. Complete schematic and initial layout.

  2. Export design (ODB++, IPC-2581) to SI/PI tool (e.g., HyperLynx, SIwave).

  3. Define simulation interfaces (I/O buffers, power supplies).

  4. Run simulations (eye diagrams, impedance profiles).

  5. Iterate layout based on results (e.g., add decoupling caps, adjust stack-up, change termination).

5.3.3 3D PCB Model Generation

• Purpose: Check mechanical clearances (enclosure, mounting, connectors), perform interference checks.

• Process: Export 3D model (STEP, Parasolid) from CAD tool. Import into mechanical CAD (SolidWorks, Creo) or dedicated viewer.

• Includes: Board outline, components (with 3D models), keep-out zones.

5.3.4 Using CAD Data for Basic Thermal Analysis

• Input: 2D/3D board geometry, material properties (copper thickness, dielectric constants), component power dissipation (from datasheets).

• Tool: Use thermal simulation modules in CAD or export to CFD tools (e.g., ANSYS Icepak).

• Output: Temperature distribution map, identification of hot spots.

5.4 Library & Database Management for Teams

Focus: Ensuring design consistency and component traceability in collaborative environments.

5.4.1 Centralized Library Management Systems

• Examples: Altium Vault, Teamcenter, Windchill.

• Function: Single source of truth for all approved components (symbols, footprints, 3D models, datasheets).

• Workflow: Designer checks out component from vault; changes require approval; vault ensures all team members use latest, approved version.

5.4.2 Component Data Management

• Managed Data per Component:

  • Logical: Symbol, footprint, 3D model.

  • Physical: Manufacturer, Part Number, Package.

  • Commercial: Supplier, Cost, Lifecycle Status (Active/Obsolete).

  • Documentation: Datasheet link, Application Notes.

• > [!TIP] Critical: Always verify lifecycle status before design finalization to avoid designing with obsolete parts.

5.4.3 Version Control for CAD

• Concept: Track changes to schematic and PCB files over time.

• Tools: Git (with LFS for binary files), SVN, or built-in CAD vault history.

• Best Practice: Commit with meaningful messages (e.g., "Added USB-C connector footprint"). Use branches for major redesigns.

5.4.4 Managing Design Revisions & Change Documentation

• Revision Control: Use built-in revision tables in schematic and PCB documents.

• Change Documentation: Create a Change Log or Engineering Change Order (ECO) detailing:

  • Revision letter (A, B, C...).

  • Description of change.

  • Affected files/components.

  • Reason for change.

  • Approval signatures.

5.5 Advanced Reporting & Automated Documentation

Focus: Automating the generation of manufacturing deliverables.

5.5.1 ⭐ Generating Fabrication & Assembly Drawings

• Fabrication Drawing (Fab Drawing):

  • Purpose: For PCB manufacturer. Shows board outline, layer stack-up, drill chart, finish, and critical dimensions.

  • Contents: Top/Bottom silkscreen, solder mask, copper layers (often as separate sheets), drill table (size, count, plated/non-plated), board outline with dimensions, notes on tolerances, testing.

  • > [!TIP] Include: Drill Drawing with all hole sizes and locations. Specify solder mask clearance and silkscreen clearance.

• Assembly Drawing ( Assy Drawing):

  • Purpose: For assembler. Shows component placement with reference designators.

  • Contents: Top and bottom views with all components outlined and labeled (RefDes). Often includes 3D view or exploded view. Highlights polarity, orientation, and any special instructions (e.g., "Do Not Populate" - DNP).

5.5.2 Automating Bill of Materials (BOM) Generation

• Process: From schematic or PCB, generate BOM report.

• Key Columns: Quantity, RefDes, Value, Part Number, Manufacturer, Description, Package, Supplier/MPN, Cost.

• Grouping: Group identical components (e.g., all 10kΩ resistors) to reduce part count and cost.

• Supplier Integration: Some tools (Altium, Octopart API) can pull live supplier data (availability, price) into BOM.

• Formats: CSV (for Excel), PDF (for documentation), XML (for ERP systems).

5.5.3 Generating Drill, Pick-and-Place & Test Point Reports

• Drill Files ( Excellon Format):

  • *.drl (drill sizes) and *.txt (drill locations).

  • Critical: Specify plated-through hole (PTH) vs. non-plated-through hole (NPTH).

• Pick-and-Place File (Centroid File):

  • CSV/Text file with X/Y coordinates (usually from board origin) and rotation angle for each component.

  • Used by SMT assembly machines.

• Test Point Report:

  • Lists all nets designated as test points, their locations (X/Y), and type (through-hole pad, via).

  • Essential for bed-of-nails testing.

5.5.4 Generating Schematic & Layout Reports

• Cross-Reference Report: Lists all components and the sheets they appear on.

• Netlist Report: Lists all nets and the pins connected to them.

• Rule Violation Report: Summary of all DRC/ERC errors/warnings.

5.6 Industry Standards & Best Practices

Focus: Adhering to global standards for reliable, manufacturable designs.

5.6.1 ⭐ IPC Standards for PCB Design

• IPC-2221: Generic standard for PCB design documentation (layer identification, drawing requirements).

• IPC-7351: Land Pattern (Footprint) Standard. Defines nominal, maximum, and minimum courtyard dimensions for surface-mount devices based on package size.

  • Density Levels:

    • Level A (Most Conservative): Highest yield, largest pads.

    • Level B (Nominal): Standard, balanced.

    • Level C (Most Aggressive): Smallest pads, for fine-pitch/high-density.

• > [!TIP] Exam Question: "Draw a footprint for a 1206 resistor according to IPC-7351 Level B." Know the Courtyard, Solder Mask, and Copper dimensions relative to the nominal component size.

5.6.2 Manufacturing Process Limitations (DFM)

• Minimum Trace/Space: Varies by fab (e.g., 3/3 mil, 4/4 mil). Always check fab house capabilities first.

• Minimum Drill Size: Typically 6-10 mil for PTH; smaller for laser drills (microvias).

• Annular Ring: Minimum copper ring around a drilled hole (e.g., 1 mil). Violation causes weak pad.

• Solder Mask Clearance: Minimum distance between solder mask and copper pad (typically 2-4 mil). Too small causes mask slivers.

• Copper Balancing: For multi-layer boards, balance copper distribution across layers to prevent warpage.

5.6.3 Design Documentation Standards for Handoff

• Complete Package Includes:

  1. Gerber Files (X2 format preferred, includes drill info).

  2. Excellon Drill Files.

  3. Pick-and-Place File.

  4. BOM.

  5. Fabrication Drawing.

  6. Assembly Drawing.

  7. Schematic (PDF).

  8. Netlist.

  9. 3D Model (if requested).

• Read Me File: Text file explaining package contents, board version, special notes.

5.6.4 ⭐ Design for Testability (DFT) Principles

• Goal: Enable efficient electrical testing of assembled boards.

• Techniques:

  • Test Points: Add unpopulated pads or vias on key nets (power, critical signals, reset lines).

  • Accessibility: Ensure test points are on one side (usually top) and not under components.

  • Bed-of-Nails Fixtures: Design with standard grid (e.g., 100mil) in mind.

  • Boundary Scan (JTAG): Incorporate JTAG chain for complex digital ICs (FPGAs, processors).

• > [!TIP] Common Mistake: Forgetting test points for power rails (+3.3V, +5V, GND). These are the first things to check.

5.7 Capstone Project Workflow: From Concept to Production Files

Focus: Holistic process integration from requirement to fabrication-ready data.

5.7.1 ⭐ Complete Project Lifecycle

1. Requirements: Define function, performance (speed, power), environmental (temperature, vibration), regulatory (FCC, CE), cost, and size targets.

2. Schematic Capture: Create hierarchical schematic. Perform ERC. Select components (consider availability, cost, footprint).

3. Component Selection & Footprint Creation: Verify/create IPC-compliant footprints. Create/assign 3D models.

4. PCB Layout:

   • Define board outline and keep-outs.

   • Place components following 5.2.5.

   • Route critical signals first (power, high-speed, clocks).

   • Apply design rules (clearance, impedance, length).

   • Run DRC continuously.

5. Verification:

   • Design Review: Checklist (schematic vs. layout, all nets connected, no unconnected pins).

   • Rule Checks: Final DRC/ERC clean.

   • SI/PI Analysis: For high-speed designs.

   • 3D Clearance Check.

6. Documentation & Output:

   • Generate all deliverables (5.5).

   • Create fabrication/assembly drawings.

   • Compile final fabrication package.

5.7.2 Comprehensive Design Review Checklist

• Schematic: All components placed? Correct values? Power/ground connections? ERC clean?

• Layout: Component orientation? Clearances met? Critical signals routed correctly? No stubs? Thermal vias under hot parts?

• Rules: All DRC violations resolved? Impedance controlled? Length matched?

• Documentation: BOM complete? RefDes unique? Fab/Assy drawings accurate? All files included in package?

5.7.3 Final Design Package Compilation

• File Formats:

  • Gerber X2: Modern format embedding drill info and layer meta-data. Prefer over RS-274X.

  • ODB++: Unified, intelligent database format (includes netlist, components, stack-up). More complete but less universal than Gerber.

  • IPC-2581: Open, intelligent standard. Most comprehensive but least universally accepted by fabs.

• > [!TIP] Recommendation: Gerber X2 + Excellon drill is the safest, most universally accepted format. Confirm with your chosen fabricator.

5.7.4 Preparing & Communicating with Fabricator/Assembler

• Request for Quote (RFQ): Provide board specs (size, layers, material like FR-4, TG), quantity, finish (HASL, ENIG), and special requirements (impedance, controlled depth routing).

• Reading Quotes: Compare not just price, but:

  • Lead time.

  • Minimum feature capabilities (trace/space, drill).

  • Testing: Flying probe vs. bed-of-nails.

  • Acceptance criteria: What defect level (e.g., IPC Class 2, 3) is assumed?

• Communication: Provide clear fabrication drawing and assembly drawing. Highlight any non-standard features (e.g., blind vias, specific impedance values, cutouts).