Electrical CAD Lab (EX-704) - Unit 2 Short Notes

UNIT 2: ELECTRICAL CAD - SCHEMATICS & SYMBOL LIBRARIES

2.1 Introduction to Electrical Schematic Design

• Purpose: A schematic diagram is a logical representation of an electrical/electronic circuit, showing components and their interconnections using standardized symbols. It is the primary design document for communication, simulation, and PCB layout.

• Key Differences:

  | Schematic Diagram | Wiring Diagram | Layout Drawing | | :--- | :--- | :--- | | Logical connectivity | Physical wiring & terminals | Physical component placement & routing | | Uses abstract symbols | Shows real-world wires, conduits | Shows copper traces, drill holes | | For design & analysis | For installation & maintenance | For manufacturing |

• Standard Design Workflow: Concept → Schematic Capture → Simulation/ERC → PCB Layout/Wiring → Documentation.

2.2 Working with Symbol Libraries

• Library Standards:

  • IEEE Std 315-1975 / IEC 60617: International standard for graphic symbols.

  • ANSI/ASME Y14.2: Common in North American practice.

  • Best Practice: Use institution/company-specific libraries built on these standards for consistency.

• Symbol Management:

  • Creating/Editing: Define pin layout, electrical pin type (Input, Output, Power, Passive), and graphical body.

  • Naming Conventions: Use clear, unique names (e.g., Resistor_Thruhole_1W, IC_Opamp_Dual).

  • Organization: Store in a centralized, version-controlled repository (e.g., Git). Use library projects.

• Placement & Wiring:

  • Place symbols from the library palette onto the schematic sheet.

  • Use Power Ports (VCC, GND) and Ground Symbols for global nets.

  • Wires (Nets): Draw direct connections. Use Bus for grouped signals (e.g., Data[0..7]) and Bus Entry to connect individual wires to a bus.

  • Off-Page Connector: Indicates a net that continues to another schematic sheet.

  • Hierarchical Block (Sheet Symbol): Represents a sub-circuit on a higher-level block diagram.

[!TIP] Common Pitfall: Never use simple graphic lines for electrical connections. Always use the "Place Wire" tool to create a net with electrical connectivity.

2.3 Schematic Design Techniques & Best Practices

• Hierarchical Design:

  • Top-Down: Start with a block diagram (hierarchical sheet symbol), then create sub-sheets for each block.

  • Benefits: Manages complexity, enables team collaboration, improves readability.

• Networking & Connectivity:

  • Netlabels: Text labels assigned to a wire segment to name the net globally (e.g., CLK, RESET). Crucial for connecting wires across hierarchy or non-physically connected sheets.

  • Power Objects: Special global nets (like VCC, GND) that connect automatically across all sheets.

  • ERC (Electrical Rule Check): Automated check for electrical errors (see 2.4).

• Documentation & BOM:

  • Designators: Unique identifiers (e.g., R1, C5, U3). Follow conventions: R=Resistor, C=Capacitor, U=IC, J=Connector.

  • Bill of Materials (BOM): Generated directly from the schematic. Contains Designator, Part Number, Description, Quantity, and Reference Designator.

  • Title Block & Revision History: Must include Project Name, Sheet#, Drawn By, Checked By, Date, Revision (A, B, 1.0, etc.).

2.4 Design Verification & Error Checking

• Electrical Rule Check (ERC):

  • Purpose: Detect electrical connection errors before PCB layout.

  • Common ERC Violations:

    1. Unconnected Pin (Input/Output): Active pin left floating.

    2. Duplicate Net Name: Two different nets incorrectly given the same label.

    3. Power Pin Conflict: Power output pin connected to another power output.

    4. Missing Power Input: IC power pin not connected to a defined power net.

  • Resolution: Run ERC, double-click errors to navigate to source, fix connectivity or pin types.

• Cross-Probing: The ability to click a schematic symbol and highlight its corresponding footprint/land pattern in the PCB layout editor (and vice-versa). Ensures schematic-to-layout consistency.

2.5 Introduction to Schematic Capture Software Tools (Generic)

• Core Interface: Project Manager (left), Workspace (center), Panels/Libraries (right), Toolbars (top).

• Essential Commands:

  • Pan (middle-click drag), Zoom (scroll), Find (Ctrl+F), Select (click/drag), Edit (double-click component).

• Project Management:

  • A project file (.PcbDoc, .kicad_sch, etc.) links all schematic sheets, libraries, and output files.

  • Version Control: Use Git or built-in tools to track changes (commit, branch, merge).

2.6 Advanced Schematic Features

• Parametric Symbols: Symbols with editable properties (e.g., a resistor where you can change Resistance and Power Rating value directly in the schematic). The footprint may update based on parameters.

• Multi-Part Components: A single physical package (e.g., 74HC00 quad NAND gate) represented as multiple schematic parts (U1A, U1B, U1C, U1D) within one component symbol.

• Hierarchical Symbols (Reusable Blocks): Create a sub-sheet (e.g., "PowerSupply"), then place a hierarchical symbol for it on the main sheet. Changes to the sub-sheet propagate everywhere it's used.

• SPICE Models: Attach a .subckt model file to a component symbol to enable circuit simulation (e.g., .model Q2N2222 NPN(...)). The schematic then becomes a simulation netlist.

2.7 Preparing Schematics for Output & Collaboration

• Plotting/Printing:

  • Plot to PDF for documentation/review.

  • Set correct scale, plot all sheets, and select "Plot to file".

  • Use "Print Preview" to check layers (usually just the Top Layer or All Layers for schematic).

• Designator Management:

  • Automatic: Tool renumbers all components sequentially (R1, R2...).

  • Manual: Used for specific numbering (e.g., R101, R102 for a specific module). Lock designators after final assignment to prevent accidental changes.

• Annotation & Revision:

  • Add text notes for clarifications.

  • Update the Revision Box in the title block with a brief description of changes.

• Netlist Export: Generates a text file listing all components and their net connections. Used as input for PCB Layout and Simulation.

  • Format Example: R1 1 2 1k (Part, Node1, Node2, Value).

• Collaboration:

  • Use Design Comments to mark issues for teammates.

  • Maintain a Review Checklist (ERC clean, BOM complete, all sheets saved).

  • Change Tracking: Some tools highlight differences between schematic versions.

2.8 Standards & Compliance in Schematic Design

• IEEE Std 315-1975 (Graphic Symbols): Defines the shape and style of symbols (e.g., resistor zigzag, capacitor parallel lines).

• IEC 60617: International standard, often uses rectangle outlines for some components (common in Europe).

• Drafting Standards: Specify:

  • Line Thickness (0.5mm for main wires, 0.25mm for auxiliary).

  • Text Height (3.5mm minimum for readability).

  • Symbol Orientation (inputs on left/right, outputs on opposite side).

  • Title Block Location (bottom right corner).

• Compliance Role: Schematics are part of technical documentation for safety certifications (e.g., UL, CE). They must be clear, unambiguous, and complete for audit.

2.9 Common Pitfalls & Troubleshooting

• Floating Nets: Wires or pins with no electrical connection to anything. Always terminate unused inputs with a defined net (e.g., pull-up to VCC or GND).

• Netlabel Misuse:

  • Wrong: Placing two netlabels with the same name on physically separate wires—they become one net, causing shorts.

  • Right: Use netlabels to intentionally connect wires across hierarchy or long distances.

• Hierarchy Naming Conflicts: Ensure unique sheet file names and unique hierarchical symbol names within a project.

• Readability Best Practices:

  • Power rails (VCC, GND) at the top/bottom.

  • Signal flow left-to-right.

  • Group related circuits together.

  • Use bus notation (Data[0..7]) instead of 8 separate wires.

  • Avoid wire crossings; use off-page connectors or hierarchical blocks.

[!TIP] Golden Rule: Run ERC frequently—after placing a few components and before any PCB layout. A clean ERC is a prerequisite for a successful design.