Microprocessor & Micro‑controller (EX-602) - Unit 5 Short Notes

I. 8086 Microprocessor

Internal Architecture (EU & BIU)

• Execution Unit (EU): Fetches, decodes, and executes instructions. Contains ALU, general registers (AX, BX, CX, DX, SP, BP, SI, DI), pointer/index registers, flag register, and control circuit.

• Bus Interface Unit (BIU): Manages all bus operations. Fetches instructions into opcode prefetch queue (6 bytes), calculates physical addresses, and generates control signals (RD, WR, M/IO, etc.).

• Pipelining: BIU fetches next instruction while EU executes current, overlapping operations for speed.

[!TIP]

Exam Focus: EU and BIU work in parallel—BIU prefetches to avoid EU wait states. Queue flushes on branch/jump instructions.

Pin Configuration

• 40-pin DIP: Multiplexed address/data bus (AD0–AD15), control signals (RD, WR, M/IO, ALE, DT/R, DEN, etc.), power/clock, interrupt pins (INTR, NMI), and mode select (MN/MX).

• Key Pins:

  • AD0–AD15: Time-multiplexed address/data.

  • A19/S6–A16/S3: Address/status lines.

  • MN/MX: Minimum (single processor) or Maximum (multi-processor) mode.

Memory Segmentation and Organization

• Segmentation: 1MB memory divided into 16 segments of 64KB each. Four segment registers: CS (code), DS (data), SS (stack), ES (extra).

• Logical Address: Segment:Offset (e.g., DS:1200H).

• Physical Address Calculation:

$$Physical\ Address = (Segment\ Register \times 16) + Offset$$

\boxed{PA = (SR \ll 4) + Offset}

Physical Address Formation

• Segment register value shifted left by 4 bits (×16) and added to 16-bit offset.

• Example: If DS = 2000H, offset 1200H → PA = 20000H + 1200H = 21200H.

Opcode Prefetch Queue

• Function: 6-byte queue in BIU stores fetched instructions. EU reads from queue instead of waiting for bus cycles.

• Significance: Overlaps fetch and execute cycles, improving performance. Queue empties on control transfers (jumps, calls), causing BIU to refill.

Stack Structure

• Type: LIFO (Last-In-First-Out), grows downward (from high to low addresses).

• Operation: PUSH decrements SP by 2, then stores word at SS:SP. POP retrieves word from SS:SP, then increments SP by 2.

• Stack Segment: Defined by SS register. Initial SP set via MOV SP, #value.

Addressing Modes (with Examples)

[!TIP]

Common Pitfall: Direct mode uses DS by default; based mode uses SS if BP is used.

Timing Diagrams (Memory Read/Write, Minimum Mode)

• Read Cycle:

  • T1: Address on AD lines, ALE high (latch address), M/IO low (memory), RD high.

  • T2: AD lines high-impedance, RD low, DT/R high (read).

  • T3: Data on AD lines, DEN low (enable buffer).

  • T4: RD high, data latched, cycle ends.

• Write Cycle:

  • T1: Address on AD lines, ALE high, M/IO low, WR high.

  • T2: Data on AD lines, WR low, DT/R low (write).

  • T3: Data valid, DEN low.

  • T4: WR high, cycle ends.

[!TIP]

Exam Focus: ALE demultiplexes address/data; DEN enables data buffers; DT/R controls direction.

System Configuration (Minimum vs Maximum Mode)

• Minimum Mode (MN/MX = 1): Single processor. 8086 generates all control signals (RD, WR, M/IO, etc.). Used in small systems.

• Maximum Mode (MN/MX = 0): Multi-processor. Uses external bus controller 8288 to generate control signals. Supports multiprocessing, DMA, and coprocessors.

Assembler Directives and Operations

Sample Assembly Programs (Outline)

1. Addition of 100 8-bit numbers:

   • Assume numbers stored in memory array.

   • Use CX = 100, SI points to array, AL accumulates sum.

   • Loop: LODSB, ADD AL, [SI], LOOP.

2. Multiply constant to sequence:

   • Constant in BL, loop through array, MUL BL (unsigned), store result.

3. Square root using lookup table:

   • Precompute squares 1–n in table. For input X, search table for value ≤ X, index gives sqrt.

4. Count positive/negative numbers:

   • Initialize counters. Loop: check sign bit (MSB), increment positive/negative counter accordingly.

II. 8051 Microcontroller

Architecture and Functional Block Diagram

• Core: 8-bit CPU with ALU, accumulator (A), B register, program counter (PC), stack pointer (SP), program status word (PSW).

• Memory: 4KB on-chip ROM (code), 128B on-chip RAM (data), Special Function Registers (SFRs).

• I/O: Four 8-bit ports (P0–P3).

• Peripherals: Two 16-bit timers/counters (T0, T1), full-duplex serial port, interrupt system (5 sources).

• Bus: External memory via P0 (multiplexed AD0–AD7) and P2 (A8–A15).

Key Features and Specifications

• 8-bit data, 16-bit address bus (64KB external memory).

• 4KB ROM, 128B RAM (expandable externally).

• 32 I/O pins (four ports), two timers, serial port.

• 5 interrupt sources with two priority levels.

• On-chip clock oscillator (12 MHz typical).

Pin Configuration (40-pin DIP)

Memory Organization

• Internal RAM (128B):

  • 00H–1FH: 32 bytes for 4 register banks (R0–R7).

  • 20H–2FH: 16 bytes bit-addressable.

  • 30H–7FH: 80 bytes general-purpose RAM.

• SFRs (80H–FFH): Special Function Registers (e.g., P0, P1, P2, P3, TCON, TMOD, SCON, IE, IP).

• External Memory: Up to 64KB each for code and data via P0/P2 and control signals (PSEN, RD, WR).

I/O Ports (P0–P3)

Interrupt Structure

• Sources: INT0 (P3.2), INT1 (P3.3), T0 overflow (TF0), T1 overflow (TF1), Serial (RI/TI).

• Registers:

  • IE (Interrupt Enable): EA (global enable), ES (serial), ET1 (timer1), EX1 (INT1), ET0 (timer0), EX0 (INT0).

  • IP (Interrupt Priority): PS, PT1, PX1, PT0, PX0 (1=high priority, 0=low).

• Priority Handling:

  1. If multiple interrupts pending, highest priority serviced first.

  2. Same priority: natural order INT0 > T0 > INT1 > T1 > Serial.

  3. High-priority interrupt can preempt low-priority.

  4. On interrupt, PC and PSW saved on stack; IE cleared to disable further interrupts unless EA set.

Addressing Modes (with Examples)

Instruction Set Overview

• Data Transfer: MOV, PUSH, POP, XCH, MOVC, MOVX.

• Arithmetic: ADD, ADDC, SUBB, INC, DEC, MUL, DIV.

• Logical: ANL, ORL, XRL, CLR, CPL, RL, RR.

• Branch: SJMP, LJMP, AJMP, JZ, JNZ, CJNE, DJNZ.

• Specific Instructions:

  • PUSH direct: Decrement SP, store direct byte at SP.

  • POP direct: Retrieve from SP, increment SP, store to direct.

  • ACALL addr11: Absolute call within 2KB page.

  • LCALL addr16: Long call to any address.

  • RET: Return from subroutine (pop PC).

  • DJNZ Rn, rel: Decrement Rn, jump if not zero.

  • SETB bit: Set bit (SFR or RAM bit).

  • CLR bit: Clear bit.

Timers/Counters (TMOD & TCON)

• TMOD (Timer Mode):

  GATE (1=timer controlled by INTx), C/T (0=timer, 1=counter), M1 M0 (mode: 00=mode0, 01=mode1, 10=mode2, 11=mode3).

• TCON (Timer Control):

  TF1 (timer1 overflow flag), TR1 (timer1 run control), TF0, TR0, IE1, IT1 (INT1 edge/level), IE0, IT0 (INT0 edge/level).

• Modes:

  • Mode 0: 13-bit timer/counter.

  • Mode 1: 16-bit timer/counter.

  • Mode 2: 8-bit auto-reload (THx holds reload value).

  • Mode 3: Timer0 split into two 8-bit timers; timer1 stopped.

Serial Communication (Modes 0–3)

[!TIP]

Compare Mode 1 vs Mode 3: Both async with start/stop bits and variable baud from timer1. Mode 3 uses 9th bit for address/data (multi-processor), mode 1 is 8-bit.

RS232 Interfacing

• Handshaking Signals:

  • RTS (Request To Send): DTE ready to transmit.

  • CTS (Clear To Send): DCE ready to receive.

  • DTR (Data Terminal Ready): DTE ready.

  • DSR (Data Set Ready): DCE ready.

  • DCD (Data Carrier Detect): Carrier detected.

  • RI (Ring Indicator): Ring detected.

• Voltage Levels: ±3 to ±15V (logic 1 = negative, 0 = positive). Use MAX232 for TTL (0–5V) conversion.

• Connection: TXD (pin 3.1) → RXD (DCE), RXD (pin 3.0) ← TXD (DCE).

Interfacing with External Devices

ADC Interfacing:

• Block Diagram:

  DiagramSEARCH: 8051 ADC interfacing circuit diagram

• Control: Start conversion via control pin (e.g., WR to ADC) or write to port. Poll EOC (End of Conversion) pin or use interrupt. Read data from ADC data pins (parallel) or via serial.

• Example: ADC0808 (8-bit, 8-channel). Connect address lines to port for channel select, START and ALE to port pins, EOC to input pin, data bus to port.

DAC Interfacing:

• Block Diagram:

  DiagramSEARCH: 8051 DAC interfacing circuit diagram

• Control: Write digital data to DAC input pins (e.g., DAC0808). Use WR pin to latch data. Output analog voltage.

• Example: Connect 8-bit data bus to P1, CS grounded, WR to P3.6.

Stepper Motor Interfacing:

• Driver Circuit: ULN2003 (Darlington array) or L293D (H-bridge). Connect motor coils to driver outputs, driver inputs to port pins.

• Step Sequence: 4-step (full step) or 8-step (half step). Example sequence: P1 = 0x01, 0x03, 0x02, 0x06, 0x04, 0x0C, 0x08, 0x09 (for unipolar).

• Control: Program delays between steps using timer.

Thyristor Firing Circuit:

• Design: Zero crossing detection (optocoupler H11AA1), firing angle control (8051 timer), opto-isolation (MOC3021), pulse transformer, thyristor (SCR/TRIAC).

• Operation: Detect AC zero crossing → start timer → after delay t_delay (firing angle), trigger MOC3021 → pulse transformer → thyristor gate.

• Timing Control: Use timer interrupt or delay loop for precise angle: t_delay = (firing angle / 360) * (1/(2*50Hz)) for 50Hz AC.

Sample Assembly Programs

1. Four arithmetic operations on two 8-bit data:

   
   MOV A, #data1    ; Load first number
   
   MOV B, #data2    ; Load second number
   
   ADD A, B         ; Addition: A = data1 + data2
   
   MOV result1, A   ; Store sum
   
   MOV A, #data1
   
   CLR C            ; Clear carry for subtraction
   
   SUBB A, B        ; Subtraction: A = data1 - data2
   
   MOV result2, A
   
   MOV A, #data1
   
   MUL AB           ; Multiplication: AB = data1 * data2
   
   MOV result3, A   ; Low byte
   
   MOV result3+1, B ; High byte
   
   MOV A, #data1
   
   DIV AB           ; Division: A = data1 / data2, B = remainder
   
   MOV result4, A   ; Quotient
   
   MOV remainder, B ; Remainder
   
   

2. Complement accumulator 900 times:

   
   MOV R2, #900     ; Counter
   
   LOOP: CPL A      ; Complement accumulator
   
   DJNZ R2, LOOP    ; Decrement and loop
   
   

III. 8096 Microcontroller

Functional Block Diagram and Explanation

• CPU: 16-bit, registers (A, B, C, D, SP, BP, SI, DI, IP, flags), ALU.

• Memory: 256B internal RAM, 8KB internal ROM (varies), external memory interface (16-bit address, 8-bit data).

• I/O: 8-bit parallel I/O ports (P0–P5), serial port.

• Timers: Two 16-bit timers (T1, T2), watchdog timer.

• A/D Converter: 10-bit, 8-channel ADC.

• PWM: Pulse Width Modulation output.

• Interrupts: 8 sources, two priority levels.

• Block Diagram:

  DiagramSEARCH: 8096 microcontroller functional block diagram

Hardware Features (vs 8051)

• 16-bit data path vs 8-bit.

• More I/O pins (up to 48), higher pin count packages.

• On-chip A/D converter (10-bit, 8-channel).

• PWM output for motor control.

• Two 16-bit timers with more modes.

• Watchdog timer for reliability.

• Higher clock speed (up to 16 MHz).

• Expanded memory: 64KB linear address space.

Memory Organization

• Memory Map: 64KB linear address space (0000H–FFFFH).

• Internal RAM: 256 bytes (00H–FFH), includes register file, bit-addressable area, general RAM.

• Internal ROM: 8KB (0000H–1FFFH) for program storage.

• External Memory: Up to 64KB each for code/data via multiplexed bus (AD0–AD7, A8–A15, RD, WR, PSEN).

Instruction Set (Classification)

• Data Transfer: MOV, PUSH, POP, XCH, LDS, LDT, STOS.

• Arithmetic: ADD, ADDC, SUB, SUBB, MUL, DIV, INC, DEC, NEG.

• Logical: AND, OR, XOR, NOT, TEST, SHL, SHR, SAR.

• Branch: JMP, JZ, JNZ, JC, JNC, CALL, RET, LOOP, DJNZ.

• Miscellaneous: NOP, HLT, SKIP, EI, DI.

Addressing Modes (with Code Examples)

Control and Status Registers (Functions)

• AD_COMMAND: A/D control (start conversion, channel select, mode).

• AD_RESULT: A/D conversion result (read-only).

• PWM_CONTROL: PWM enable, polarity, period.

• TIMER_CONTROL: Timer enable, mode, prescaler.

• I/O_PORT: Data direction and output for ports.

• INTERRUPT_MASK: Enable/disable interrupt sources.

• STATUS: Flags (carry, zero, overflow) and peripheral status.

IV. Programmable Peripheral Interface (8255)

Block Diagram and Internal Architecture

• Block Diagram:

  DiagramSEARCH: 8255 PPI block diagram

• Architecture:

  • Three 8-bit ports: Port A, Port B, Port C (split into upper/lower nibbles).

  • Control Register: Sets modes and I/O direction.

  • Data Bus Buffer: 8-bit bidirectional interface to CPU.

  • Read/Write Logic: Manages control signals (RD, WR, CS, A0, A1).

Modes of Operation

Control Word Format and Interpretation

• Mode Set Flag: D7 = 1 for mode set, 0 for bit set/reset (Port C).

• Control Word Bits:

  
  D7: 1 = Mode Set
  
  D6 D5: Port A mode (00=0, 01=1, 1x=2)
  
  D4: Port A direction (1=output)
  
  D3: Port C upper (1=output)
  
  D2: Port B mode (0=0, 1=1)
  
  D1: Port B direction (1=output)
  
  D0: Port C lower (1=output)
  
  

• Example: Control word 10011000B (98H):

  • D7=1 → Mode set.

  • D6D5=00 → Port A Mode 0.

  • D4=1 → Port A output.

  • D3=1 → Port C upper output.

  • D2=0 → Port B Mode 0.

  • D1=0 → Port B input.

  • D0=0 → Port C lower input.

  • Answer: i) Mode 0, ii) Input, iii) Upper output, lower input.

V. Programmable Interval Timer (8254)

Internal Architecture and Block Diagram

• Block Diagram:

  DiagramSEARCH: 8254 PIT block diagram

• Architecture:

  • Three independent 16-bit counters (Counter 0, 1, 2).

  • Control Register: Write-only, selects counter, mode, read/write format.

  • Read/Write Logic: Interfaces with data bus.

  • Counter Blocks: Each has latch, counter, output logic.

Modes of Operation (0–5)

VI. DMA Controller (8257)

Block Diagram and Operation

• Block Diagram:

  DiagramSEARCH: 8257 DMA controller block diagram

• Operation: Transfers data between I/O and memory without CPU intervention. Channels 0–3, each with address and word count registers.

• Transfer Modes:

  • Demand: Transfer until DREQ low.

  • Single: One byte/word per request.

  • Block: Transfer entire block.

  • Cascade: For multi-chip expansion.

Registers

• Command Register: Enable channels, fixed/rotating priority, memory address increment/decrement.

• Status Register: Interrupt flags, terminal count status.

• Mode Register: Channel mode (demand/single/block/cascade), address increment, autoinitialization.

• Base Address/Word Count Registers: Per channel, reloaded after transfer if autoinit.

Priority Management

• Fixed Priority: Channel 0 highest, 3 lowest.

• Rotating Priority: Priority rotates after each transfer, fair sharing.

Control Signals

• HRQ (Hold Request): To CPU for bus control.

• HLDA (Hold Acknowledge): From CPU, grants bus.

• DREQ (DMA Request): From I/O device.

• DACK (DMA Acknowledge): To I/O device, grants access.

• MEMR, MEMW: Memory read/write.

• IOR, IOW: I/O read/write.

VII. USART (8251)

Block Diagram and Functional Description

• Block Diagram:

  DiagramSEARCH: 8251 USART block diagram

• Functional Blocks:

  • Transmitter: Parallel-to-serial converter, buffer, shift register.

  • Receiver: Serial-to-parallel converter, shift register, buffer.

  • Control Unit: Mode instruction, command instruction, status read.

  • Data Bus Buffer: Interface to CPU.

  • Modem Control: Handshaking signals (CTS, RTS, DSR, DTR).

Operation and Modes

• Synchronous Mode:

  • External clock synchronizes transmission.

  • Data transmitted on clock edge, no start/stop bits.

  • Character length 5–8 bits, parity optional.

• Asynchronous Mode:

  • Start bit (0), 5–8 data bits, optional parity, stop bit(s) (1 or 1.5/2).

  • Baud rate from internal/external clock.

  • Mode 1: 8-bit data, 1 start, 1 stop, variable baud.

  • Mode 2: 9-bit data (multiprocessor), fixed baud (fosc/64 or /32).

  • Mode 3: 9-bit data, variable baud (like mode 1).

VIII. I/O Mapping Techniques

Memory-Mapped I/O

• Concept: I/O devices assigned memory addresses. CPU uses MOV instructions to access.

• Address Space: Uses part of memory address space.

• Advantages: Full instruction set available, easy to program, no special I/O instructions.

• Disadvantages: Reduces available memory, slower if memory wait states.

Isolated/Peripheral-Mapped I/O

• Concept: Separate I/O address space, accessed via IN/OUT instructions.

• Address Space: Dedicated I/O ports (e.g., 64K in x86).

• Advantages: Does not consume memory space, dedicated control signals (IOR, IOW).

• Disadvantages: Limited instructions, requires special I/O instructions.

Comparison

IX. Interfacing Applications (with 8051)

ADC Interfacing

• Block Diagram:

  DiagramSEARCH: 8051 ADC0808 interfacing diagram

• Control:

  • Select channel via address lines (P1.0–P1.2).

  • Pulse START and ALE to begin conversion.

  • Poll EOC pin (low during conversion, high when done) or use interrupt.

  • Read data from ADC data pins (P0) when EOC high.

• Example Code:

  
  MOV P1, #00H      ; Select channel 0
  
  SETB P3.0         ; ALE = 1
  
  CLR P3.0          ; ALE = 0, latch address
  
  SETB P3.1         ; START = 1
  
  CLR P3.1          ; START = 0, start conversion
  
  WAIT: JNB P3.2, WAIT ; Wait for EOC (P3.2 high)
  
  MOV A, P0         ; Read data
  
  

DAC Interfacing

• Block Diagram:

  DiagramSEARCH: 8051 DAC0808 interfacing diagram

• Control:

  • Write digital data to DAC input pins (e.g., P1).

  • Pulse WR (P3.6) to latch data.

  • Output analog voltage proportional to input.

• Example: Connect DAC0808 data pins to P1, CS grounded, WR to P3.6.

RS232 Serial Communication Interfacing

• Voltage Level Conversion: Use MAX232 to convert TTL (0–5V) to RS232 (±12V).

• Connection:

  • 8051 TXD (P3.1) → MAX232 T1IN → RS232 TXD.

  • RS232 RXD → MAX232 R1OUT → 8051 RXD (P3.0).

  • Handshaking signals (RTS, CTS, etc.) via other port pins if needed.

• Baud Rate: Set timer1 for desired baud (e.g., 9600 bps at 11.0592 MHz).

Stepper Motor Interfacing

• Driver Circuit: ULN2003 (7 Darlington pairs) or L293D (H-bridge).

• Connection: Motor coils to driver outputs, driver inputs to P1.0–P1.3.

• Step Sequence (4-step full step):

  
  Step 1: P1 = 0x01 (0001)
  
  Step 2: P1 = 0x03 (0011)
  
  Step 3: P1 = 0x02 (0010)
  
  Step 4: P1 = 0x06 (0110)
  
  Step 5: P1 = 0x04 (0100)
  
  Step 6: P1 = 0x0C (1100)
  
  Step 7: P1 = 0x08 (1000)
  
  Step 8: P1 = 0x09 (1001)
  
  

• Control: Use timer interrupt for delays between steps (e.g., 10 ms/step).

Thyristor Firing Circuit

• Design:

  • Zero Crossing Detection: Optocoupler H11AA1 detects AC zero crossing, outputs pulse.

  • Firing Angle Control: 8051 timer measures delay from zero crossing to trigger pulse.

  • Isolation: MOC3021 (optotriac) drives pulse transformer gate.

  • Power: TRIAC/SCR for AC load.

• Accurate Timing: Use timer interrupt on zero-cross pulse. Calculate delay:

$$t_{delay} = \frac{firing\ angle}{360} \times \frac{1}{2 \times line\ frequency}$$

For 50Hz, period = 20ms, half = 10ms. For 90° angle, delay = 2.5ms.

• Circuit:
  DiagramSEARCH: 8051 thyristor firing circuit diagram

X. Advanced Microcontrollers

16-bit PIC Microcontrollers

• Architecture: Harvard, 16-bit data, 24-bit instruction word (PIC24/dsPIC33).

• Features: Up to 40 MIPS, 16-bit ALU, 16×16 multiplier, rich peripherals (ADC, DAC, PWM, CAN, USB).

• Instruction Set: 16-bit instructions, 16 registers (R0–R15), compiler-friendly.

32-bit PIC Microcontrollers

• Architecture: MIPS32 core (PIC32MX), 32-bit data/address.

• Features: Up to 80 MHz, 512KB flash, 128KB RAM, Ethernet, USB, graphics, RTCC.

• Applications: High-performance embedded (audio, video, networking).

DSPIC Microcontrollers

• Architecture: 16-bit PIC with DSP engine (dsPIC30/33).

• Features: 16-bit data, 24-bit instructions, 16×16 MAC unit, barrel shifter, zero-overhead looping.

• Applications: Digital signal processing (motor control, audio, filters).

[!TIP]

Exam Focus: Compare PIC16 (8-bit), PIC24/dsPIC (16-bit), PIC32 (32-bit) on data width, speed, peripherals.