UNIT 4: MICROPROCESSOR & MICROCONTROLLER (EXAM-FOCUSED SHORT NOTES)

I. 8086 MICROPROCESSOR

A. Internal Architecture & Functional Units

The 8086 has a two-bus architecture to enable parallel instruction fetch and execution.

• Bus Interface Unit (BIU): Manages all external bus operations.

  • Components: Segment registers (CS, DS, SS, ES), Instruction Pointer (IP), Address Adder (generates 20-bit physical address), Instruction Queue (6-byte FIFO prefetch queue).

  • Role: Fetches instructions, reads/writes operands from/to memory/I/O, calculates physical addresses.

• Execution Unit (EU): Executes instructions.

  • Components: ALU (16-bit), General Purpose Registers (AX, BX, CX, DX), Flag Register (16-bit), Control Circuit.

  • Role: Decodes instructions, executes them using ALU and registers, updates flags.

• Coordination (Pipelining): While EU executes current instruction, BIU fetches and queues subsequent instructions. Overlap improves speed. EU pauses if queue is empty or a branch occurs.

[!TIP] Exam Key: EU and BIU work in parallel. The opcode prefetch queue (6 bytes) is the key to this pipelining. If EU needs a bus cycle (e.g., for a memory operand), BIU stalls the fetch.

B. Memory Organization & Segmentation

• Concept: 8086 uses segmentation to overcome 16-bit register limitation for addressing 1MB (2^20 bytes) memory.

• Segments: Four active segments at a time, each 64KB max, defined by segment registers:

  • CS (Code Segment): Holds program instructions.

  • DS (Data Segment): Holds data.

  • SS (Stack Segment): Holds stack.

  • ES (Extra Segment): Additional data segment (often for string operations).

• Physical Address Formation:

$$Physical\ Address = (Segment\ Register \times 10H) + Offset$$

Offset is 16-bit from IP, BX, SI, DI, etc. Result is 20-bit (1MB range: 00000H to FFFFFH).

• Addressing: Any physical location can be accessed via multiple segment:offset pairs (e.g., CS:IP, DS:BX).

C. Addressing Modes

[!TIP] Common Pitfall: In Based/Indexed modes, BP defaults to SS, others default to DS. Use segment override prefix (MOV AX, ES:[BX]) to change.

D. Stack Structure

• LIFO (Last-In-First-Out) structure in Stack Segment (SS).

• Stack Pointer (SP): 16-bit register holding offset of top of stack within SS.

• Operation: PUSH decrements SP by 2 (word), stores data at SS:SP. POP reads from SS:SP, increments SP by 2.

• Word vs. Byte: 8086 stack is word-oriented (16-bit). PUSH/POP always operate on words. Use PUSHF/POPF for flags.

E. Pin Configuration & System Modes

• Key Pins (Multiplexed Address/Data): AD0-AD15 (multiplexed address/data). A19/S6-A16/S3 (high address/status). BHE/S7 (Bus High Enable/status).

• Control Signals: RD (Read), WR (Write), M/IO (Memory/I/O), DT/R (Data Transmit/Receive), DEN (Data Enable), READY (Wait state), INTR (Interrupt Request), NMI (Non-Maskable Interrupt), RESET.

• MN/MX Pin: Determines system mode.

  • Minimum Mode (MN/MX=1): 8086 generates all control signals itself. For single-processor systems.

  • Maximum Mode (MN/MX=0): Requires external bus controller (8288). For multi-processor/multi-master systems. Status signals S0-S2 used by 8288.

F. Timing Diagrams (Minimum Mode)

Memory Read Cycle (T1-T4):

1. T1: AD0-AD15 carry low address (A0-A15). A19/S6-A16/S3 carry high address (A16-A19). ALE goes HIGH to latch address.

2. T2: AD0-AD15 float (high-impedance). RD goes LOW. DT/R LOW (read mode). DEN becomes active (LOW) to enable data bus.

3. T3: Data from memory appears on AD0-AD15. READY must be HIGH; if LOW, wait states (Tw) inserted.

4. T4: RD and DEN go HIGH. Data is read by 8086. Cycle ends.

Memory Write Cycle:

Similar, but WR goes LOW instead of RD. DT/R is HIGH (write mode). Data must be stable on bus in T2.

[!TIP] Exam Focus: Be able to draw and label waveforms for T1-T4 states, showing ALE, RD/WR, DT/R, DEN, AD0-AD15 (address in T1, data in T3/T4, float in T2), and status signals.

G. Assembly Language Programming (Examples)

• Series Addition (100 numbers):

  
  MOV CX, 100       ; Counter
  
  MOV SI, OFFSET ARRAY ; Point to array
  
  XOR AX, AX        ; Clear sum
  
  CLD               ; Forward direction
  
  REPEAT: LODSW      ; Load word from [SI] to AX, inc SI by 2
  
  ADD SUM, AX       ; Add to SUM
  
  LOOP REPEAT       ; Dec CX, jump if not zero
  
  

• Lookup Table (Square Root): Store precomputed squares in table. Use index (e.g., MOV AL, [TABLE + BX] where BX holds number).

• Counting Positives/Negatives: Use SIGN flag after ADD/SUB or test MSB. Increment positive/negative counters accordingly.

H. Assembler Directives & Operators

• Data Definition: DB (Define Byte), DW (Define Word), DD (Define Doubleword).

• Segment Definition: SEGMENT (start segment), ENDS (end segment), ASSUME (tell assembler which segment register for which segment).

• Operators: OFFSET (returns offset of label), EQU (equate - defines constant), GROUP (combines segments).

II. 8051 MICROCONTROLLER

A. Architecture & Pin Diagram

• Functional Blocks: 8-bit CPU, ALU, Accumulator (A), B register, Program Status Word (PSW), 128/256-byte Internal RAM, 4/8KB Internal ROM/EPROM, 4 I/O Ports (P0-P3), 2 16-bit Timers (T0, T1), Full-Duplex UART, Interrupt System.

• Pin Description:

  • P0: Multiplexed Address/Data bus (needs external pull-ups). ALE pulses to separate address.

  • P1: Pure I/O (no alternate function).

  • P2: High byte of address bus for external memory.

  • P3: I/O with alternate functions (/INT0, /INT1, T0, T1, WR, RD).

  • /EA: External/Internal Memory select (1=internal, 0=external).

  • /PSEN: Program Store Enable (read from external ROM).

  • RST: Reset input (active HIGH, must be HIGH for 2 machine cycles).

  • XTAL1/2: Crystal oscillator connections.

B. Memory Organization in Detail

• Internal RAM (128/256 bytes):

  • 00-1FH: 32 bytes for 4 register banks (R0-R7). Selected by PSW.3-4 (RS1, RS0).

  • 20-2FH: 16 bytes bit-addressable area (128 bits). Each byte can be addressed as bits (e.g., SETB 20H sets bit 0 of 20H).

  • 30-7FH/FFH: General purpose RAM (scratchpad).

• Special Function Registers (SFRs): Addresses 80H-FFH. Not all addresses used. Control ports, timers, serial, interrupts (e.g., P0=80H, TMOD=89H, SCON=98H, IE=A8H, IP=B8H).

• External Memory: Up to 64KB each for data and program. Uses P0 (multiplexed) and P2 for address, RD/WR for control. ALE latches low address from P0.

C. Addressing Modes

[!TIP] Critical Distinction: @R0/@R1 can only access internal RAM (00-7FH). To access external RAM, use MOVX A, @DPTR or MOVX A, @R0 (with R0/R1 as 8-bit page address, DPTR as full 16-bit).

D. Instruction Set Overview (Key Instructions)

• Data Transfer: MOV (all modes), PUSH/POP (only direct addresses, use SP), XCH (exchange), MOVC (code memory), MOVX (external memory).

• Arithmetic: ADD/ADDC (with carry), SUBB (with borrow), INC/DEC, MUL/DIV (A and B only).

• Logical: ANL, ORL, XRL, CLR, CPL (A or direct bit).

• Control Transfer: JZ/JNZ (check A), CJNE (compare & jump), DJNZ (decrement & jump), ACALL/LCALL, RET/RETI.

• Bit Manipulation: SETB, CLR, CPL (on bit-addressable SFRs/IRAM). JB/JNB/JBC (jump on bit).

E. Interrupt Structure & Priority

• Sources (5): /INT0 (P3.2), /INT1 (P3.3), Timer0 Overflow (TF0), Timer1 Overflow (TF1), Serial (RI/TI).

• Enable Register (IE - A8H):

  • EA (Global enable)

  • ES (Serial), ET1 (Timer1), EX1 (/INT1), ET0 (Timer0), EX0 (/INT0).

• Priority Register (IP - B8H): Bits set to 1 = high priority, 0 = low priority. Natural priority (if same level): /INT0 > T0 > /INT1 > T1 > Serial.

• Vector Addresses: Each interrupt has fixed 8-bit address (e.g., /INT0=0003H, T0=000BH). On interrupt, PC pushed, PC loaded with vector, IE.0-5 cleared (except for level-triggered /INTx).

• RETI: Returns from interrupt, restores PC and re-enables interrupt evaluation.

F. Timers/Counters (T0, T1)

• Registers:

  • TMOD (89H): Mode control. Format: GATE C/T M1 M0 for each timer.

    • M1 M0: Mode (00=0, 01=1, 10=2, 11=3).

    • C/T: 0=Timer (internal clock), 1=Counter (external pulses on T0/T1 pin).

    • GATE: 0=Timer controlled by TRx, 1=Timer also controlled by /INTx pin (for pulse width measurement).

  • TCON (88H): Control & flags.

    • TF1, TF0: Timer overflow flags (set by hardware, cleared by software).

    • TR1, TR0: Timer run control bits (1=start).

    • IE1, IE1: External interrupt edge flags.

• Modes (Focus on 1 & 2):

  • Mode 1 (16-bit Timer): THx and TLx form 16-bit timer. Max count = 65536.

  • Mode 2 (8-bit Auto-Reload): TLx holds count, THx holds reload value. On overflow, TLx=THx automatically. Good for baud rate generation.

  • Mode 0 (13-bit), Mode 3 (two 8-bit): Less common.

G. Serial Communication (UART)

• SCON (98H) Register:

  • SM0, SM1: Mode select (00=Mode0, 01=Mode1, 10=Mode2, 11=Mode3).

  • SM2: Multiprocessor mode enable (Modes 2/3).

  • REN: Receive enable (1=enable).

  • TB8: 9th bit for transmission (Modes 2/3).

  • RB8: 9th bit received (Modes 2/3).

  • TI: Transmit interrupt flag (set on TB8 sent, cleared by software).

  • RI: Receive interrupt flag (set on RB8 received, cleared by software).

• Mode Comparison:

  | Mode | Type | Data Bits | Start/Stop | Clock Source | 9th Bit | Baud Rate | | :--- | :--- | :--- | :--- | :--- | :--- | :--- | | 0 | Sync | 8 | No | Internal (fosc/12) | N/A | Fixed | | 1 | Async | 8 | 1 start, 1 stop | Timer1 overflow | N/A | Variable (Timer1) | | 2 | Async | 9 | 1 start, 1 stop | Internal (fosc/32) | Yes (TB8) | Fixed (fosc/32) | | 3 | Async | 9 | 1 start, 1 stop | Timer1 overflow | Yes (TB8) | Variable (Timer1) |

• Baud Rate (Mode 1/3):

$$Baud\ Rate = \frac{2^{SMOD}}{32} \times \frac{F_{osc}}{12 \times (256 - TH1)}$$

where SMOD is bit in PCON (power control register).

H. Interfacing & Applications

• ADC Interfacing: 8051 has no internal ADC. Use external chip (e.g., ADC0808/0809).

  • Parallel Interface: Connect 8-bit data bus to P1. Control signals (START, ALE, OE, EOC) from P3/P2. Program: Start conversion, poll/ wait for EOC, read data from P1.

• DAC Interfacing: Use parallel DAC (e.g., DAC0800).

  • Connect 8-bit data from P1 to DAC inputs. CS and WR from P3/P2. Output analog voltage proportional to digital input.

• RS-232 Interfacing:

  • Need: Convert TTL (±5V) to RS-232 (±12V). Use MAX232 level shifter (charge pump).

  • Handshaking: RTS (Request To Send), CTS (Clear To Send), DTR (Data Terminal Ready), DSR (Data Set Ready). Used for flow control between DTE (PC) and DCE (modem).

• Stepper Motor Interfacing:

  • Unipolar (5/6 wire): Common center tap. Use ULN2003 (Darlington array) driver to sink current from coils.

  • Sequence: Half-step or full-step sequence generated by 8051 on P1/P3. Delay between steps controls speed (use Timer delay).

• Thyristor Firing Circuit:

  • Need: Phase control of AC power (e.g., light dimmer, motor speed).

  • Zero-Crossing Detection: Use opto-coupler (e.g., MOC3041) to detect AC zero-crossing, generate interrupt to 8051.

  • Firing Angle Control: 8051 calculates delay from zero-cross to firing pulse (based on desired angle). Generate pulse via another opto-coupler (MOC) to trigger SCR/Triac.

III. PROGRAMMABLE PERIPHERAL INTERFACE CHIPS

A. 8255A PPI

• Functional Blocks: Data Bus Buffer (8-bit), Control Logic, Group A (Port A + upper Port C), Group B (Port B + lower Port C).

• Modes of Operation:

  • Mode 0 (Basic I/O): Simple input/output. No handshaking. Ports A, B, C ( halves) can be input or output.

  • Mode 1 (Strobed I/O): Handshaking for input/output. Uses Port C bits (STB, IBF, OBF, ACK). Port A or B only. Other port in Mode 0.

  • Mode 2 (Bidirectional Bus): Only for Port A. Uses all 5 Port C bits for handshaking (bidirectional data bus).

• Control Word Format:

  • I/O Mode: 1 (Mode set). D2 D1 D0 define Port A, C upper, Port B modes.

  • BSR Mode: 0 (Bit Set/Reset). D3 D2 D1 D0 select Port C bit to set/reset.

  • Example: 10011000B (98H)

    • 1 -> I/O Mode.

    • 001 -> Port A: Mode 1 Output.

    • 1 -> Port C Upper: Output.

    • 000 -> Port B: Mode 0 Input.

    • 0 -> Port C Lower: Input (implied by Port B Mode 0 input).

B. 8257 DMA Controller

• Functional Blocks: 4 independent DMA channels (CH0-CH3). Each has:

  • DMA Address Register (16-bit): Holds source/destination memory address.

  • DMA Word Count Register (16-bit): Holds number of transfers. Decrements after each transfer.

  • Control Logic: Prioritizes requests, generates bus control signals.

• Operation:

  1. Peripheral asserts DREQ (DMA Request).

  2. 8257 requests bus from CPU via HRQ (Hold Request).

  3. CPU releases bus, responds with HLDA (Hold Acknowledge).

  4. 8257 becomes bus master. It places address from channel's address register on address bus, activates MEMR/MEMW and IOR/IOW based on transfer direction.

  5. Data transferred. Word count decremented.

  6. If count ≠ 0, repeat. If count = 0, Terminal Count (TC) bit set for that channel, channel disabled (unless auto-initialize).

• Priority Schemes:

  • Fixed: CH0 > CH1 > CH2 > CH3.

  • Rotating: Priority rotates after each service cycle.

• Signals: HRQ, HLDA, DREQ0-3, DACK0-3, MEMR, MEMW, IOR, IOW.

C. 8254 Programmable Interval Timer (PIT)

• Functional Blocks: 3 independent 16-bit down counters (Counter 0,1,2). Each has:

  • Data Register (Read/Write): Holds count value.

  • Control Register (Write-only): Selects counter, read/write format, mode, BCD/binary.

• Control Word Format: SC1 SC0 | RW1 RW0 | M2 M1 M0 | BCD

  • SC1 SC0: Select Counter (00=0, 01=1, 10=2, 11=Read-Back - 8254-2 only).

  • RW1 RW0: Read/Write (00=Latch, 01=Read/Write LSB, 10=Read/MSB, 11=Read/Write LSB then MSB).

  • M2 M1 M0: Mode (0-5).

  • BCD: 0=Binary, 1=BCD.

• Key Modes:

  • Mode 0: Interrupt on Terminal Count. Output goes HIGH after count reaches 0.

  • Mode 2: Rate Generator. Periodic square wave. Auto-reload.

  • Mode 3: Square Wave (similar to 2, 50% duty cycle).

  • Mode 4: Software Triggered Strobe. Single pulse after count.

  • Mode 5: Hardware Triggered Strobe. Pulse after GATE trigger.

• Applications: Event counter, real-time clock (Mode 2/3), baud rate generator (Mode 2), tone generation.

D. 8251 USART

• Functional Blocks: Transmitter, Receiver, Baud Rate Generator, Control/Status Logic.

• Modes:

  • Synchronous: Data transmitted continuously with clock. Can be internal (clock from baud gen) or external (clock from RxC pin). 5-8 data bits. Sync character(s) transmitted.

  • Asynchronous: Start-stop bits. 5-8 data bits, optional parity, 1 or 2 stop bits.

• Key Registers (accessed via same address, RD/WR pins differentiate):

  • Data Buffer: Read (receive data) or Write (transmit data).

  • Control/Status: Write (control word), Read (status bits: TxRDY, RxRDY, TxEMPTY, PE, OE, FE).

• Handshaking: /CTS (Clear To Send - input), /RTS (Request To Send - output), /DSR (Data Set Ready), /DTR (Data Terminal Ready). Used for flow control.

• Interfacing: Connects to 8086/8051 data bus. Control/status registers at fixed I/O addresses. TxRDY/RxRDY can generate interrupts.

IV. 8096 MICROCONTROLLER & ADVANCED ARCHITECTURES

A. 8096 Functional Block Diagram & Superiority

• Blocks: 16-bit CPU, 232-byte internal RAM, 8KB internal ROM, 8-channel 10-bit ADC, 2 PWM outputs, 5 16-bit timers (T1-T5), Watchdog Timer, Serial Port (UART), Interrupt Controller, I/O Ports (P0-P4).

• Superiority over 8051:

  • 16-bit data path & ALU (faster arithmetic).

  • Integrated high-performance peripherals: ADC (10-bit, 8-ch), PWM (2-ch), more timers.

  • Higher memory: 8KB ROM, 232B RAM (vs 4KB/128B).

  • Better interrupt system: More sources, priority levels.

  • Designed for embedded control: Motor control, data acquisition.

B. Memory Organization & Instruction Set

• Memory Map:

  • Internal RAM: 00H-E7H (232 bytes). Includes register file, SFRs, scratchpad.

  • Internal ROM: 0FF00H-1FFFFH (8KB). Contains system monitor/application code.

  • External Memory: Up to 64KB data space (at 00H-FFFFH), 64KB program space (at FF00H-FFFFH can be external if EA=0).

• Instruction Set Classification:

  • Data Transfer: LDB, LDW, STB, STW, PUSH, POP, LDB/STB with indexed addressing.

  • Arithmetic/Logical: ADD, SUB, MUL, DIV, AND, OR, XOR, SHL, SHR.

  • Branch: JMP, Jcc (conditional), JC, JNC, JE, JNE, JL, JGE, DJNZ.

  • Bit Manipulation: SETB, CLR, CPL, JB, JNB.

  • Control: NOP, HALT, IDLE, RESET, ENABLE/DISABLE interrupts.

• Addressing Modes (Examples):

  • Immediate: LDW R0, #1234H

  • Direct: LDW R0, 2000H (internal RAM address)

  • Indirect: LDW R0, @R1 (R1 holds address)

  • Indexed: LDW R0, 1000H(R1) (Effective addr = 1000H + R1)

  • Relative: JMP LABEL (PC-relative)

  • Implied: NOP

C. Control & Status Registers (Key SFRs)

• I/O Port Registers: P0-P4 (write 1s to configure as input). P0-P3 have alternate functions.

• ADC Control/Status: AD_CTRL (start conversion, select channel), AD_RESULT (read result).

• Timer Control/Status: T1CON, T2CON, etc. (enable, mode, gate control). T1STATUS, T2STATUS (overflow, interrupt flags).

• PWM Control: PWM_CTRL (enable, polarity), PWMx registers (duty cycle).

• Interrupt Registers: IP (Interrupt Priority), IM (Interrupt Mask). INT_PEND (pending interrupts).

• System Configuration: CCR (CPU Control - clock, wait states, watchdog).

V. I/O INTERFACING TECHNIQUES & SYSTEM DESIGN

A. Memory-Mapped I/O vs. Isolated (Peripheral-Mapped) I/O

B. General Interfacing Concepts

• Address Decoding: Use decoders (e.g., 74LS138 3-to-8) to select a device based on high-order address lines. Ensures each I/O/memory chip responds to a unique address range.

• Data Bus Buffering: Use transceivers (74LS245/244) to isolate peripheral data bus from processor bus, prevent bus contention, provide drive capability.

• Wait State Generation: For slow peripherals, insert wait states (READY pin in 8086, ALE stretching in 8051) to synchronize timing.

C. Application-Oriented Systems

• 8051-based Thyristor Firing Circuit:

  1. Zero-Crossing Detection: Opto-coupler (MOC3041) connected to AC line generates interrupt at each zero-crossing.

  2. Firing Angle Calculation: On interrupt, 8051 starts a timer. After delay t_delay = (α/360) * T_line, 8051 triggers another opto-coupler (MOC) connected to SCR gate.

  3. Isolation: Both opto-couplers provide electrical isolation between high-voltage AC and low-voltage 8051.

• Stepper Motor Interfacing:

  1. Motor: Unipolar (5/6 wire) or bipolar (4 wire).

  2. Driver: ULN2003 (Darlington array) or L293D (H-bridge for bipolar). 8051 port pins drive ULN2003 inputs.

  3. Sequence: 8051 outputs step sequence (e.g., full-step: 1010 -> 0110 -> 0101 -> 1001 -> repeat) on port pins.

  4. Speed Control: Insert delay between steps using Timer interrupt or software loop.

[!TIP] Exam Focus: Be prepared to draw block diagrams for thyristor firing and stepper motor interfacing, labeling all components (8051, opto-couplers, SCR/Triac, driver IC, motor) and signal flow.