UNIT 3: Microprocessor & Microcontroller

I. 8086 MICROPROCESSOR

A. Internal Architecture & Functional Units

The 8086 has a two-stage pipelined architecture consisting of:

• Bus Interface Unit (BIU): Handles all bus operations (address generation, instruction fetch, read/write). Contains:

  • Segment Registers (CS, DS, SS, ES): Hold base addresses of 64KB segments.

  • Instruction Pointer (IP): Holds offset of next instruction in CS.

  • Address Adder: Computes 20-bit physical address.

  • Prefetch Queue (6-byte): Stores fetched instructions to overlap fetch-execute cycles.

• Execution Unit (EU): Decodes & executes instructions. Contains:

  • ALU: 16-bit arithmetic/logic operations.

  • General Purpose Registers (AX, BX, CX, DX): Can be used as 16-bit or 8-bit (AH/AL, etc.).

  • Pointer/Index Registers (SP, BP, SI, DI): For stack, base, source, destination.

  • Flag Register: Status flags (CF, PF, AF, ZF, SF, TF, IF, DF, OF).

• EU-BIU Interaction: While EU executes current instruction, BIU fetches next instructions into queue. If EU needs a bus cycle (e.g., for a memory operand), BIU pauses prefetching.

[!TIP] Exam Focus: Be prepared to draw the block diagram and explain the pipelining advantage (performance boost by overlapping cycles).

B. Memory Organization & Segmentation

• Segmentation Concept: 8086 generates 20-bit addresses to access 1MB (2^20) memory but uses 16-bit registers. Solution: segment:offset addressing.

  • Four 64KB segments: Code (CS), Data (DS), Stack (SS), Extra (ES).

  • Default segment registers: MOV from memory uses DS; PUSH/POP uses SS; STRING ops use DS:SI/ES:DI; instruction fetch uses CS:IP.

• Physical Address Formation:

$$\text{Physical Address} = (\text{Segment Register Value} \times 16) + \text{Offset}$$

> Example: For `DS = 2000H` and offset `1200H`, Physical Addr = `(2000H * 10H) + 1200H = 21200H`.

• Memory Interleaving: 1MB memory often organized as two 512KB banks (even/odd addresses) to allow faster access by using both banks simultaneously.

C. Addressing Modes

[!TIP] Exam Focus: Always specify the default segment register for memory operands in your examples.

D. Instruction Set & Programming (Key Examples)

• Data Transfer: MOV (reg/mem), PUSH/POP (word only), XCHG, IN/OUT (isolated I/O).

• Arithmetic/Logical: ADD/SUB/INC/DEC, MUL/DIV (unsigned, use AX/AL), AND/OR/XOR/NOT, CMP (sets flags, no result).

• Branch/Loop: JMP (unconditional), Jcc (conditional on flags), LOOP (decrement CX, jump if ≠0), JCXZ (jump if CX=0).

• String: MOVSB/CMPSB/SCASB/LODSB/STOSB operate on [SI]/[DI]. Use REP prefix for repetition.

• Programming Patterns:

  • Series Addition (16-bit): Use ADD with carry, loop with LOOP.

  • Look-up Table: Use XLAT (AL = [BX+AL]) or indexed addressing.

  • Complement Accumulator N Times: MOV CX, N; AGAIN: CPL A; LOOP AGAIN.

E. Stack Structure

• LIFO structure. PUSH decrements SP by 2, writes word; POP reads word, increments SP by 2.

• Stack Segment (SS): Defines 64KB segment. Stack grows downward (towards lower addresses).

• Word-Aligned: SP always even. Best performance when SP is aligned on a paragraph boundary (SP % 16 = 0).

• Interrupt Handling: On interrupt, FLAGS, CS, IP pushed onto stack (in that order). IRET pops them back.

F. Timing Diagrams & System Operation (Minimum Mode)

• Read Cycle (Memory or I/O read):

  1. T1: Address on AD0-AD15, ALE goes high (latch address), M/IO high (memory) or low (I/O).

  2. T2: AD bus tristated, RD goes low, DEN enables data bus buffer.

  3. T3: Data must be valid on bus. READY sampled; if low, wait state (Tw) inserted.

  4. T4: RD goes high, data latched by 8086.

• Write Cycle:

  1. T1: Address on bus, ALE high, M/IO set.

  2. T2: WR goes low, data driven onto AD bus by 8086, DEN enables buffer.

  3. T3: Data must be held. READY checked for wait states.

  4. T4: WR goes high, ends cycle.

• Minimum vs. Maximum Mode: Minimum mode (MN/MX#=1) uses 8086's own control logic. Maximum mode (MN/MX#=0) uses external bus controller (8288) for multi-processor systems.

G. I/O & Interfacing Concepts

• Memory-Mapped I/O:

  • I/O devices occupy a portion of memory address space.

  • Use MOV instructions for access.

  • M/IO signal is high during access.

  • Advantage: Full instruction set available. Disadvantage: Reduces available memory.

• Isolated (Peripheral-Mapped) I/O:

  • Separate 16-bit I/O address space (64KB).

  • Use IN/OUT instructions.

  • M/IO signal is low during access.

  • Advantage: Memory space untouched. Disadvantage: Limited instructions, special control signals.

• Assembler Directives:

  • DB (Define Byte), DW (Define Word), DD (Define Doubleword).

  • EQU (Equate - assign constant to label).

  • ORG (Origin - set location counter).

  • ASSUME (Tell assembler about segment registers).

II. 8051 MICROCONTROLLER

A. Architecture & Pin Configuration

• Functional Blocks:

  • CPU: 8-bit ALU, Accumulator (A), B register, PSW (Program Status Word).

  • Memory: 4KB on-chip ROM/Flash (program), 128/256B on-chip RAM (data).

  • I/O Ports: Four 8-bit ports (P0-P3). P0 & P2 used as address/data bus for external memory.

  • Timers: Two 16-bit timers/counters (T0, T1).

  • Serial Port: Full-duplex UART.

  • Interrupts: 5 sources (2 external, 2 timers, 1 serial).

  • Clock: Internal oscillator (XTAL1/XTAL2).

• Pin Diagram Key:

  • RST: Reset input (high for 2 machine cycles).

  • ALE: Address Latch Enable (for demultiplexing P0).

  • PSEN: Program Store Enable (read from external ROM).

  • EA: External Access (high=use internal ROM first).

B. Memory Organization

• Program Memory: 0000H to FFFFH. If EA=1, internal ROM (0000-0FFFH) used first; external ROM beyond.

• Data Memory:

  • Internal RAM (128/256B):

    • 00H-1FH: 4 register banks (R0-R7).

    • 20H-2FH: 16 bytes, bit-addressable (128 bits).

    • 30H-7FH: General purpose RAM.

    • 80H-FFH: Special Function Registers (SFRs) (if 256B RAM).

  • External RAM (up to 64KB): Accessed via MOVX using DPTR or @Ri.

• SFR Map (Key Registers):

  • P0, P1, P2, P3 (0x80, 0x90, 0xA0, 0xB0): I/O ports.

  • TCON (0x88), TMOD (0x89): Timer control.

  • SCON (0x98), SBUF (0x99): Serial control & buffer.

  • IE (0xA8), IP (0xB8): Interrupt enable/priority.

  • DPTR (0x82, 0x83): Data pointer (16-bit).

C. Addressing Modes (8051 Specific)

D. Instruction Set Overview (Classification)

• Data Transfer: MOV (reg, direct, indirect, immediate), MOVC (code memory), MOVX (external RAM), PUSH/POP (SFRs only), XCH/XCHD.

• Arithmetic: ADD/ADDC/SUBB, INC/DEC, DA (Decimal Adjust), MUL/DIV (A*B->AB).

• Logical: ANL/ORL/XRL, CLR/CPL (bit/accumulator), RL/RR/RLC/RRC (rotate/shift).

• Branch: ACALL/LCALL/RET, AJMP/LJMP/SJMP, JZ/JNZ, CJNE (compare & jump if not equal), DJNZ (decrement & jump).

• Bit Manipulation: SETB/CLR/CPL (bit), JB/JNB/JBC (jump if bit set/not set/clear).

• Control: NOP.

E. Timers/Counters

• Registers:

  • TMOD (Timer Mode): Format GATE C/T M1 M0 | GATE C/T M1 M0 (for T1/T0).

    • M1,M0: Mode select (00=Mode0, 01=Mode1, 10=Mode2, 11=Mode3).

    • C/T: 0=Timer (internal clock), 1=Counter (external pulses on T0/T1 pin).

    • GATE: 1=Timer runs only when INT0/1 pin is high.

  • TCON (Timer Control): TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0.

    • TRx: Timer Run control bit (1=start).

    • TFx: Timer Overflow flag (interrupt if set & ETx=1).

• Modes:

  • Mode 0: 13-bit timer (THx:8 bits + TLx:5 bits).

  • Mode 1: 16-bit timer (THx:TLx as full 16-bit).

  • Mode 2: 8-bit auto-reload (TLx counts, reloads from THx on overflow).

  • Mode 3: T0 split into two 8-bit timers; T1 stopped (if used as baud rate).

• Example (Delay using Mode 1): Load TH0/TL0 with calculated value for desired delay. Start with SETB TR0. Poll TF0 or use interrupt.

F. Serial Communication

• UART: Asynchronous, full-duplex. Data framed with start bit, 8 data bits, optional parity, stop bit(s).

• SCON Register (Serial Control):

  
  SM0 SM1 SM2 REN TB8 RB8 TI RI
  
  

  • SM0,SM1: Mode select (00=Mode0, 01=Mode1, 10=Mode2, 11=Mode3).

  • SM2: Multiprocessor mode enable.

  • REN: Receive Enable (1=enable).

  • TB8/RB8: 9th data bit (for Mode 2/3).

  • TI: Transmit Interrupt flag (set when SBUF empty).

  • RI: Receive Interrupt flag (set when byte in SBUF).

• Modes:

  | Mode | Description | Data Bits | Clock Source | Baud Rate | | :--- | :--- | :--- | :--- | :--- | | 0 | Synchronous, shift register | 8 | Fosc/12 | Fixed | | 1 | 8-bit UART | 8 | Timer1 overflow | Variable | | 2 | 9-bit UART | 9 | Fosc/32 or /64 | Fixed | | 3 | 9-bit UART | 9 | Timer1 overflow | Variable |

• Mode 1 vs. Mode 3:

  • Similarity: Both 8-bit data, variable baud rate from Timer1.

  • Difference: Mode 3 uses 9th bit (TB8/RB8) for multi-processor communication (address/data packets).

  • Apps: Mode 1 for standard async comm; Mode 3 for networks where 9th bit distinguishes address (1) from data (0).

• Baud Rate (Mode 1/3): Baud Rate = (2^(SMOD) / 32) * (Timer1 Overflow Rate). Timer1 usually in Mode 2 (8-bit auto-reload).

• RS-232 Interfacing: 8051 TTL levels (0-5V) ≠ RS-232 (±3 to ±15V). Use MAX232 level shifter (charge pump). Handshaking (RTS/CTS) optional for flow control.

G. Interrupt System

• 5 Sources & Vectors:

  | Source | Flag | Vector (Hex) | Priority (Natural) | | :--- | :--- | :--- | :--- | | External 0 (INT0) | IE0 | 0003H | 1 (Highest) | | Timer 0 (TF0) | TF0 | 000BH | 2 | | External 1 (INT1) | IE1 | 0013H | 3 | | Timer 1 (TF1) | TF1 | 001BH | 4 | | Serial (RI/TI) | RI/TI | 0023H | 5 (Lowest) |

• Registers:

  • IE (Interrupt Enable): EA ES ET1 EX1 ET0 EX0. EA=1 global enable.

  • IP (Interrupt Priority): PS PT1 PX1 PT0 PX0. 1=high priority, 0=low.

• Priority Handling:

  1. Fixed Priority: If IP.x=1 for a source, it's high priority; else low.

  2. Within same priority: Natural order (IE0 > TF0 > IE1 > TF1 > RI/TI) decides which interrupt is serviced first if multiple pending.

  3. On Interrupt: Current PC (2 bytes) and PSW pushed to stack. ISR at vector address. RETI pops PC/PSW and clears priority latch.

• Interrupt Response Time: ~3-8 machine cycles (depends on current instruction, other interrupts).

H. Interfacing with External Devices

• ADC Interfacing:

  • Need: Convert analog sensor voltage to digital for microcontroller.

  • Interface: ADC has control pins (CS, RD, WR, EOC). Start conversion by pulsing WR. Wait for EOC (poll or interrupt). Read data via MOVX A, @DPTR.

  • Example Code: CLR P3.4 (CS=0); SETB P3.6; CLR P3.6 (start); WAIT: JNB P3.7, WAIT (check EOC); MOVX A, @DPTR; SETB P3.4.

• DAC Interfacing:

  • Need: Convert digital value to analog (e.g., for control, waveform generation).

  • Interface: Load digital data to DAC's input latch via MOVX @DPTR, A. DAC output voltage Vout = (Vref * D) / 256 (for 8-bit).

  • Circuit: R-2R ladder network inside DAC.

• Stepper Motor Interfacing:

  • Motor: Unipolar (5/6 wire) or Bipolar (4 wire). Requires sequence of pulses on coils.

  • Drive: Use ULN2003/ULN2803 (Darlington array) to provide current.

  • Control: Use a port (e.g., P1) to output sequence. Timer interrupt generates precise pulse timing (delay between steps).

• Thyristor Firing Circuit:

  • Application: AC power control (light dimmer, motor speed).

  • Circuit: Zero-crossing detector (optocoupler) detects AC zero. Microcontroller (8051) counts half-cycles. After desired delay (phase angle), trigger pulse sent via optocoupler (MOC) to thyristor gate.

  • Accurate Timing: Use Timer interrupt to measure delay from zero-crossing to firing pulse. Phase angle = (Delay / Half-cycle period) * 180°.

III. PROGRAMMABLE PERIPHERAL INTERFACE CHIPS

A. 8255A PPI

• Functional Blocks:

  • Data Bus Buffer: 8-bit bidirectional interface to CPU data bus.

  • Control Logic: Decodes CPU control signals (RD, WR, A0, A1).

  • Ports A, B, C: 8-bit I/O ports. Port C can be split into two 4-bit ports.

• Control Word Format:

  • Mode Set (D7=1): Defines ports A, B, C modes.

    
    D7 D6 D5 D4 D3 D2 D1 D0
    
    1  |PA Mode| |PB Mode| |PC Upper| |PC Lower|
    
    PA Mode: 00=Mode0, 01=Mode1, 10=Mode2 (only PA), 11=Mode1 (PC handshaking).
    
    PC Upper/Lower: 0=output, 1=input.
    
    

  • Bit Set/Reset (D7=0): Controls individual bits of Port C.

    
    D7 D6 D5 D4 D3 D2 D1 D0
    
    0  | 1 | | Bit Select | | 0/1 (Set/Reset) |
    
    

• Modes:

  • Mode 0 (Basic I/O): Simple input/output. Port C can provide handshaking signals (PC3-PC0 for Port B, PC7-PC4 for Port A).

  • Mode 1 (Strobed I/O): Handshaking for input/output. Uses Port C bits for STB, IBF, ACK, OBF. Interrupts possible.

  • Mode 2 (Bidirectional Bus): Only for Port A. Uses Port C for handshaking (8-bit bidirectional data bus).

• Example: Control Word 10011000B = 90H.

  • D7=1 → Mode Set.

  • PA Mode = 00 (Mode 0), PB Mode = 01 (Mode 1), PC Upper = 1 (input), PC Lower = 00 (output).

  • Ans: i) Mode 0, ii) Port B is output (Mode 1 output implied), iii) Port C upper=input, lower=output.

B. 8257 DMA Controller

• Functional Blocks: Channel Priority Encoder, 4 independent channels (each with SAR, DAR, TCR), Data Buffer, Control Logic, Address Generation.

• Registers per Channel:

  • SAR (Source Address Register): Holds source memory/I/O address.

  • DAR (Destination Address Register): Holds destination address.

  • TCR (Transfer Count Register): Counts number of transfers (decremented to zero).

• Priority Schemes:

  • Fixed Priority: CH0 > CH1 > CH2 > CH3 (highest to lowest).

  • Rotating Priority: (Conceptual) Priority changes after each cycle to share bus fairly.

• Control Signals & Operation:

  • HRQ (Halt Request): 8257 asks CPU to release bus.

  • HLDA (Halt Acknowledge): CPU grants bus (floats its buses).

  • DREQx (DMA Request): Peripheral requests transfer on channel x.

  • DACKx (DMA Acknowledge): 8257 acknowledges request, enables peripheral.

  • TC (Terminal Count): Output goes high when TCR=0 for a channel.

• Operation: CPU programs SAR, DAR, TCR. On DREQ, 8257 gets HRQ/HLDA. Then it performs read-from-source/write-to-dest cycles, auto-incrementing addresses/decrementing TCR. Stops on TC or DREQ deassertion. Returns bus with HLDA low.

C. 8254 Programmable Interval Timer

• Functional Blocks: Data Bus Buffer, Read/Write Logic, Control Register, 3 independent Counters (0,1,2).

• Counter Internal Structure: Each counter has:

  • Control Word Register (write-only): Sets mode, read/write format, counter select.

  • Status Register (read-only via Read-Back command): Holds current count, state, mode.

  • 16-bit Count Register: Actual down-counter.

• Operating Modes (6):

  | Mode | Description | Typical Use | | :--- | :--- | :--- | | 0 | Interrupt on Terminal Count | One-shot, event detection | | 1 | Hardware Retriggerable One-Shot | Pulse generation | | 2 | Rate Generator | Square wave, periodic interrupt | | 3 | Square Wave Generator | Symmetrical square wave (like Mode 2 but 50% duty) | | 4 | Software Triggered Strobe | Delayed strobe | | 5 | Hardware Triggered Strobe | External trigger strobe |

• Read/Write Operations:

  • Write: Latch first (LSB or MSB), then second byte.

  • Read: Use Latch Count command to freeze count for stable reading.

  • Read-Back Command: Read status & count simultaneously.

• Applications: Baud rate generator (Mode 2), real-time clock (cascaded counters), event counter.

D. 8251 USART

• Functional Blocks:

  • Transmitter: Parallel-to-serial converter, shift register, parity generator.

  • Receiver: Serial-to-parallel converter, shift register, parity checker.

  • Data Bus Buffer: Interface to CPU.

  • Control/Status Registers: Mode, Command, Status.

• Registers:

  • Mode Instruction: Sync/async, character size (5-8 bits), parity (even/odd/stick), stop bits (1,1.5,2).

  • Command Instruction: TxEN, RxEN, DTR, RTS, SBRK (send break), RxC (receive clock source).

  • Status Register: TxRDY (transmitter ready), RxRDY (receiver ready), TxE (transmitter empty), PE (parity error), OE (overrun error), FE (framing error), SYNDET/BRK (sync detect/break).

• Synchronous vs. Asynchronous:

  • Synchronous: Clock shared, data transmitted continuously, character-oriented, CRC error check. Used for high-speed, short distances.

  • Asynchronous: Start/stop bits framing each character, independent clocks, variable baud rate. Used for RS-232.

• Handshaking: Uses RTS (Request to Send) and CTS (Clear to Send) for flow control. DTR/DSR for modem control.

IV. ADVANCED MICROCONTROLLERS

A. 8096 (80C196) Microcontroller

• Superiority over 8051:

  • 16-bit data path & ALU (vs 8-bit).

  • Register-to-register architecture (faster, no accumulator bottleneck).

  • Higher clock speed (~16 MHz vs 12 MHz).

  • More on-chip peripherals: Event Processor Array (EPA) for high-speed I/O, 10-bit A/D (8/16 channels), Watchdog Timer, enhanced UART.

  • Better interrupt system: 8-level priority, multiple vector addresses.

• Functional Block Diagram:

  • CPU: 16-bit, 8-bit & 16-bit operations, 8x8 multiplier.

  • Memory Interface: 16-bit data bus, 16-bit address (A0-A15). Can interface external memory directly.

  • I/O Ports: P0-P6 (some multiplexed with address/data bus).

  • Timers: Two 16-bit timers (Timer1 can be 2 x 8-bit).

  • EPA: 6-8 capture/compare/PWM channels with dedicated timers.

  • A/D Converter: 10-bit, 8/16 channel multiplexer.

  • Serial Port: Full-duplex UART.

  • Watchdog Timer: System safeguard.

• Memory Organization:

  • Internal RAM: 232 bytes (register file, 16-bit/8-bit accessible).

  • External Memory: Up to 64KB each for data & program. Uses RD, WR, ALE, PSEN.

  • Memory Status Register (MSB): Configures chip selects for external memory banks.

• Instruction Set Classification:

  • Data Transfer: MOV (register, direct, indirect, immediate), PUSH/POP, XCH.

  • Arithmetic/Logical: ADD/SUB/MUL/DIV, AND/OR/XOR, shifts/rotates.

  • Branch: JMP, Jcc, LOOP, JCXZ.

  • Bit Manipulation: SETB/CLR/CPL, JB/JNB.

  • Control: NOP, RESET.

  • String: MOVS, CMPS, SCANS, LODS, STOS (with REP).

  • Peripheral: Instructions for Timer, EPA, A/D (e.g., LD to timer registers).

• Addressing Modes:

  • Register: ADD AX, BX.

  • Direct: MOV AX, [1234H] (16-bit direct address).

  • Indirect: MOV AX, [BX], [BP], [SI], [DI].

  • Indexed: MOV AX, [BX+10H] (based-indexed).

  • Relative: JMP SHORT label.

  • Immediate: MOV AX, #1234H.

• Control & Status Registers:

  • I/O Control: Port configuration registers (P0-P6 control) set direction (input/output).

  • Interrupt Control:

    • IPR (Interrupt Pending Register): Bits set when source requests.

    • IMR (Interrupt Mask Register): Mask bits (1=masked).

    • IPR2 (Interrupt Priority Register): 3-bit priority per source (0-7).

  • Timer/Event Control: TCW (Timer Control Word) sets mode, TSR (Timer Status) shows flags.

  • A/D Control: AD_CTRL (start, mode), AD_RESULT (read-only).

B. PIC & dsPIC Microcontrollers

• 16-bit PIC (e.g., PIC24, dsPIC33):

  • Architecture: Harvard, modified RISC (mostly single-cycle instructions).

  • Key Features: 16-bit data, 24-bit instruction width, 8x8 hardware multiplier, DMA, multiple nested interrupts (up to 7 levels), low-power modes.

  • Memory: Flash (program), SRAM (data), EEPROM (non-volatile data).

  • Peripherals: Enhanced Capture/Compare/PWM (ECCP), high-speed ADC (10/12-bit), multiple UART/SPI/I2C, CAN, USB.

• 32-bit dsPIC (Digital Signal Controller):

  • dsPIC33 vs PIC24: Adds DSP engine:

    • 40-bit accumulator (40-bit wide).

    • Barrel shifter.

    • Signed/unsigned fractional arithmetic.

    • Special MAC (Multiply-Accumulate) instructions.

  • Target Apps: Motor control, power conversion, audio, industrial control (where DSP needed).

  • Performance: Up to 40 MIPS, 16-bit data, 24-bit instructions.

V. CROSS-CUTTING & APPLICATION TOPICS

A. I/O Techniques Deep Dive

B. Interfacing Applications Summary

• ADC/DAC:

  • ADC: Start conversion (WR pulse), wait for EOC, read data (MOVX). Use interrupt on EOC for efficiency.

  • DAC: Load data (MOVX) to DAC latch. Output analog voltage proportional to digital value.

• Stepper Motor:

  • Circuit: Port → ULN2003 → Stepper coils.

  • Code: Look-up table for step sequence. Timer interrupt for step delay (speed control).

• Thyristor Firing:

  • Circuit: Zero-cross detector (opto) → 8051 interrupt → Count half-cycles → After delay, send firing pulse via opto (MOC) to thyristor gate.

  • Accuracy: Timer interrupt ensures precise phase angle control independent of code execution time.

• RS-232:

  • Voltage Levels: RS-232 uses ±3 to ±15V; 8051 uses 0-5V TTL.

  • MAX232: Charge pump converts TTL ↔ RS-232 levels.

  • Handshaking: RTS (Request to Send) from DTE (8051), CTS (Clear to Send) from DCE (modem) to prevent data overrun.

Final Note: Always draw diagrams where possible (block diagrams, pin diagrams, timing waveforms). For programming questions, write clean code with comments. For calculations (physical address, baud rate, timer reload), show formula and substitution.