UNIT 2: Microprocessor & Microcontroller - Comprehensive Short Notes

Based on analysis of 5 years of past question papers (2022-2025), this unit covers 8086 Microprocessor, Programmable Peripheral Devices (8255, 8254, 8257, 8251), 8051 Microcontroller, and 8096 Microcontroller. The 8051 and 8086 are the highest frequency topics.

I. 8086 MICROPROCESSOR (Highest Frequency - Core Focus)

A. Architecture & Internal Organization

The 8086 has a two-stage pipelined architecture consisting of:

1. Bus Interface Unit (BIU): Handles all bus operations (address generation, memory/I/O access, instruction prefetch). It contains:

   • Instruction Pointer (IP)

   • Segment Registers (CS, DS, SS, ES)

   • Address Adder (for physical address calculation)

   • Instruction Queue (6-byte FIFO)

2. Execution Unit (EU): Executes instructions. It contains:

   • General Purpose Registers (AX, BX, CX, DX)

   • Pointer/Index Registers (SP, BP, SI, DI)

   • ALU, Control Circuitry

   • Flag Register (FLAGS)

Key Separation: BIU fetches instructions into the queue while EU executes them, enabling overlapping operations (pipelining).

[!TIP] Exam Focus: Be prepared to draw the functional block diagram and clearly distinguish the roles of EU and BIU. Questions often ask about the significance of the prefetch queue.

B. Memory Organization & Addressing

• Segmentation: 8086 uses a segmented memory model. The 20-bit physical address is formed from a 16-bit segment register and a 16-bit offset:

$$Physical\ Address = (Segment\ Register \times 10H) + Offset$$

The segment value is shifted left by 4 bits (multiplied by 16) and added to the offset.

• Stack Structure: Stack grows downward in memory. It is defined by the Stack Segment (SS) register and Stack Pointer (SP) register.

  • PUSH decrements SP by 2, then stores data at SS:SP.

  • POP reads data from SS:SP, then increments SP by 2.

  • The stack can be up to 64KB (limited by SS).

C. Addressing Modes

[!TIP] Common Pitfall: Forgetting that [ ] denote memory access. MOV AX, [SI] means "move the contents of the memory location whose offset is in SI to AX".

D. Timing & Control (Minimum Mode)

In Minimum Mode, the 8086 generates all control signals itself. Key timing signals for a Memory Read Cycle:

1. T1: Address is put on the address bus (latched by ALE).

2. T2: Address bus is tristated, control signals (RD, M/IO) become active. Data bus is driven by memory.

3. T3: Data is read from the bus by the 8086.

4. T4: RD goes inactive, cycle ends.

Key Control Signals:

• RD (Read), WR (Write): Active low.

• M/IO (Memory/I/O): High for memory, low for I/O.

• ALE (Address Latch Enable): Indicates valid address on bus.

• DEN (Data Enable): Enables transceivers.

• DT/R (Data Transmit/Receive): Controls bus direction.

[!TIP] Exam Focus: You must be able to derive and draw the timing diagram for a memory read/write cycle in minimum mode, labeling ALE, RD/WR, M/IO, and data validity.

E. Pin Configuration & System Design

• Pin Diagram: 40-pin DIP. Key pins: AD0-AD15 (multiplexed address/data), A16-A19/S6-S3 (status lines), BHE/S7, RD, WR, M/IO, DT/R, DEN, ALE, READY, TEST, INTR, NMI, RESET.

• Minimum Mode System: Used with a single processor. Control signals (RD, WR, M/IO, ALE, DEN, DT/R) are generated by the 8086. Requires address latches (e.g., 8282) and bus transceivers (e.g., 8286).

• Assembler Directives: Pseudo-ops that tell the assembler how to organize the program (e.g., ASSUME, ORG, DB, DW, EQU, END).

F. Programming Applications

• Loops: Use LOOP, JCXZ instructions.

• Look-up Tables: Use XLAT instruction or indexed addressing ([BX+AL]).

• Series Operations: Use REP prefix with string instructions (MOVSB, STOSB) for block transfers.

• Conditional Counting: Compare each element and increment a counter based on sign flag (SF) or zero flag (ZF).

• Square Root using Lookup Table: Pre-store square roots in a table. For input N, load AL=N, set BX=offset(table), execute XLAT to get result in AL.

II. PROGRAMMABLE PERIPHERAL DEVICES (High Frequency)

A. 8255A Programmable Peripheral Interface (PPI)

• Functional Block: Three 8-bit ports (A, B, C). Port C can be split into two 4-bit parts. Control logic interprets control word.

• Operating Modes:

  • Mode 0 (Basic I/O): Simple input/output. No handshaking.

  • Mode 1 (Strobed I/O): Uses handshaking signals (STB, IBF, OBF, ACK). Ports A & B can operate; Port C provides control signals.

  • Mode 2 (Bidirectional Bus): Only for Port A. Uses Port C for handshaking (INTR, IBF, OBF, STB, ACK). Allows data flow in both directions.

• Control Word Format:

  
  D7 D6 D5 | D4 D3 | D2 D1 D0
  
  Mode Sel | Port A/B | Port C Upper/Lower
  
  

  • D7=1 for I/O mode, D7=0 for BSR mode (set/reset individual bits of Port C).

  • D6,D5: Mode selection for Port A.

  • D4: Port A direction (1=Input, 0=Output).

  • D3: Port B direction.

  • D2: Port C Upper (PC4-PC7) direction.

  • D1,D0: Mode selection for Port B.

  • D0: Port C Lower (PC0-PC3) direction.

• Example: Control word 10011000B (98H):

  • D7=1 → I/O Mode.

  • D6D5=00 → Port A in Mode 0.

  • D4=1 → Port A is Input.

  • D3=0 → Port B is Output.

  • D2=1 → PC Upper (PC4-PC7) is Input.

  • D1D0=00 → Port B in Mode 0.

  • D0=0 → PC Lower (PC0-PC3) is Output.

B. 8254 Programmable Interval Timer (PIT)

• Internal Architecture: Three independent 16-bit counters (Counter 0, 1, 2). Each counter has:

  • Data Register (read/write)

  • Control Word Register

  • Read/Write Logic

  • Counter Logic (preset, decrement, output generator)

• Operating Modes (0-5):

  • Mode 0: Interrupt on Terminal Count. Output goes high after count reaches zero.

  • Mode 1: Hardware Retriggerable One-Shot. Output goes low on gate pulse, returns high after count.

  • Mode 2: Rate Generator. Periodic square wave output.

  • Mode 3: Square Wave Generator (symmetrical). Similar to Mode 2 but 50% duty cycle.

  • Mode 4: Software Triggered Strobe. Output low for one clock after count.

  • Mode 5: Hardware Triggered Strobe. Like Mode 4 but triggered by gate.

• Control Word Format:

  
  D7 D6 | D5 D4 | D3 D2 D1 D0
  
  Counter Select | Read/Write | Mode | BCD/Binary
  
  

  • D7-D6: Select counter (00=C0, 01=C1, 10=C2, 11=Read-Back - 8254 only).

  • D5-D4: Access mode (00=Latch, 01=LSB only, 10=MSB only, 11=LSB then MSB).

  • D3-D1: Operating mode (0-5).

  • D0: Count format (0=Binary, 1=BCD).

C. 8257 DMA Controller

• Block Diagram: 4 independent DMA channels (CH0-CH3). Each channel has:

  • DMA Address Register (16-bit, holds memory address)

  • Terminal Count Register (16-bit, lower 14 bits hold count, upper 2 bits hold mode info)

  • Mode Set Register (8-bit, global)

• Priority Management:

  • Fixed Priority: CH0 > CH1 > CH2 > CH3.

  • Rotating Priority: Priority changes after each cycle (last used gets lowest).

  • Selected by D7 bit in Mode Set Register (0=Fixed, 1=Rotating).

• DMA Transfer Cycle:

  1. Processor releases bus (HLDA goes low).

  2. DMA controller asserts DREQ for highest priority requesting channel.

  3. Controller sends HRQ to processor, waits for HLDA.

  4. Controller drives address bus, sends DACK to device, and controls MEMR/MEMW signals for read/write cycle.

  5. After transfer, decrements TC register. If TC=0 and auto-initialize is off, channel is disabled.

• Key Control Signals:

  • HRQ (Hold Request), HLDA (Hold Acknowledge): To processor.

  • DREQ (DMA Request), DACK (DMA Acknowledge): To/from peripheral.

  • MEMR, MEMW: Memory read/write control.

D. 8251 USART (Universal Synchronous/Asynchronous Receiver/Transmitter)

• Functional Block: Transmitter and Receiver sections, each with:

  • Data Buffer (Transmit/Receive)

  • Control/Status Registers

  • Baud Rate Generator (for asynchronous mode)

  • Synchronization logic (for synchronous mode)

• Operating Modes:

  • Synchronous Mode: Data transmitted continuously with sync characters. Clock is provided externally or internally. Used for block data transfer.

  • Asynchronous Mode: Data framed by start/stop bits. Character length (5-8 bits) and parity configurable. Clock derived from baud rate generator.

• Handshaking for RS232: Uses RTS (Request to Send), CTS (Clear to Send), DSR (Data Set Ready), DTR (Data Terminal Ready) for flow control.

• Baud Rate Generation: Internal generator uses an external clock and a programmable divisor. Baud rate = Clock Frequency / (Divisor × 16).

E. I/O Techniques

[!TIP] Exam Focus: 8051 uses Memory-Mapped I/O (ports are part of memory map). 8086 can use either, but often uses Peripheral-Mapped for I/O chips.

III. 8051 MICROCONTROLLER (Very High Frequency)

A. Architecture & Pin Configuration

• Functional Block Diagram: Central 8-bit CPU with on-chip peripherals (4 I/O ports, 2 timers, serial port, interrupt system). All connected via an internal bus.

• Pin Diagram (40-pin DIP):

  • Pins 1-8: Port 1 (P1.0-P1.7), pure I/O.

  • Pins 9-16: Port 3 (P3.0-P3.7), dual function (I/O + alternate functions like RXD, TXD, INT0, INT1, T0, T1, WR, RD).

  • Pins 17-20: Port 2 (P2.0-P2.7), dual function (I/O + high byte of external memory address).

  • Pins 21-28: Port 0 (P0.0-P0.7), dual function (I/O + multiplexed low byte of address/data bus for external memory).

  • Pins 29-31: Control pins (EA/VPP, ALE/PROG, PSEN).

  • Pins 32-39: VSS, XTAL2, XTAL1, RST, VDD.

B. Memory Organization

• Program Memory: Internal (4KB ROM/EPROM in 8051) at addresses 0000H-0FFFH. External up to 64KB if EA=0.

• Data Memory:

  • Internal RAM (128 bytes): 00H-7FH (general purpose, bit-addressable), 80H-FFH (SFRs).

  • External RAM (up to 64KB): Accessed via MOVX instructions.

• External Memory Interfacing: ALE latches low byte from P0. PSEN (Program Store Enable) reads external ROM. RD/WR control external RAM. P2 provides high address byte.

C. Addressing Modes

D. Instruction Set Overview (Key Instructions from Past Papers)

• Data Transfer: MOV, PUSH, POP, XCH, MOVC, MOVX.

• Arithmetic: ADD, ADDC, SUBB, INC, DEC, MUL, DIV, DA A.

• Logical: ANL, ORL, XRL, CPL, CLR, SETB.

• Branch: JZ, JNZ, JC, JNC, SJMP, AJMP, LJMP, ACALL, LCALL, RET, RETI.

• Control: NOP, CLR A, CPL A, SWAP.

Specific Instructions:

• PUSH direct: Decrement SP, store direct byte at SP.

• POP direct: Read byte from SP, increment SP, store in direct.

• ACALL addr11: Absolute call within 2KB page.

• LCALL addr16: Long call anywhere in 64KB.

• RET: Return from subroutine (pop PC from stack).

• DJNZ Rn, rel: Decrement register, jump if not zero.

• SETB bit: Set a bit (in RAM or SFR).

E. Special Function Registers (SFRs)

• Accumulator (ACC/A): Primary register for ALU operations, I/O, and most instructions.

• B Register: Used for MUL/DIV and as a second accumulator.

• Program Status Word (PSW):

  
  CY AC F0 RS1 RS0 OV - P
  
  

  • CY: Carry flag.

  • AC: Auxiliary Carry (for BCD).

  • F0: Flag 0 (user definable).

  • RS1,RS0: Register Bank select (0-3).

  • OV: Overflow flag.

  • P: Parity flag (even parity).

• Stack Pointer (SP): Points to top of stack (internal RAM). Initialized to 07H after reset.

• Data Pointer (DPTR): 16-bit register for external memory addressing (MOVX @DPTR, A).

• Power Control (PCON): Contains SMOD (double baud rate) and idle/power-down bits.

F. Interrupt Structure

• 5 Interrupt Sources:

  1. INT0 (External Interrupt 0) - Vector 0003H

  2. T0 (Timer 0 Overflow) - Vector 000BH

  3. INT1 (External Interrupt 1) - Vector 0013H

  4. T1 (Timer 1 Overflow) - Vector 001BH

  5. RI/TI (Serial Port) - Vector 0023H

• Interrupt Enable (IE) Register:

  
  EA ES ET1 EX1 ET0 EX0
  
  

  • EA: Global enable (must be 1).

  • EX0, ET0, EX1, ET1, ES: Individual enables.

• Interrupt Priority (IP) Register:

  
  - - PT1 PX1 PT0 PX0
  
  

  • PX0, PT0, PX1, PT1: Set for high priority, clear for low.

• Priority Handling:

  1. If two interrupts of same priority occur, fixed priority order: INT0 > T0 > INT1 > T1 > Serial.

  2. If a high-priority interrupt occurs while a low-priority one is being serviced, the high-priority one wins.

  3. A high-priority interrupt cannot be interrupted by another high-priority one (except by INT0/INT1 if edge-triggered and new edge arrives).

  4. On interrupt, current PC and PSW are pushed to stack, corresponding interrupt flag is cleared (except for edge-triggered INTx), service routine at vector address executes.

• Response Sequence: Interrupt Acknowledgment → Push PC/PSW → Clear flag (if level-triggered) → Jump to vector.

G. Timers/Counters

• Registers: TH0/TL0 (Timer 0), TH1/TL1 (Timer 1).

• TMOD Register (Timer Mode):

  
  GATE C/T M1 M0 | GATE C/T M1 M0
  
  (For T1)       | (For T0)
  
  

  • GATE: Gate control (1=Timer runs only while INT pin is high).

  • C/T: Counter/Timer select (0=Timer, 1=Counter).

  • M1,M0: Mode selection (0,1,2,3).

• TCON Register (Timer Control):

  
  TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
  
  

  • TF1,TF0: Timer overflow flags (set by hardware, cleared by software).

  • TR1,TR0: Timer run control bits (1=start).

  • IE1,IE1: External interrupt edge flags.

  • IT1,IT0: Interrupt type (1=edge-triggered, 0=level-triggered).

• Operating Modes:

  • Mode 0: 13-bit timer (THx: 8 bits, TLx: 5 bits).

  • Mode 1: 16-bit timer (THx:TLx as 16-bit).

  • Mode 2: 8-bit auto-reload (TLx counts, THx holds reload value).

  • Mode 3: (Timer 0 only) T0 split into two 8-bit timers; T1 stopped.

• Programming Example (Delay): Load THx/TLx with calculated value for desired delay. Set TMOD, start TRx. Wait for TFx flag, then clear it.

H. Serial Communication

• Serial Port Block Diagram: Shift register, baud rate generator, control logic (SCON), buffer (SBUF).

• Modes of Operation:

  • Mode 0: Shift Register (8-bit, synchronous, fixed baud rate = fosc/12). Used for I/O expansion.

  • Mode 1: 8-bit UART, variable baud rate (Timer 1 overflow rate / 32 or /16 if SMOD=1). Start bit, 8 data bits, stop bit.

  • Mode 2: 9-bit UART, fixed baud rate (fosc/64 or /32 if SMOD=1). 9th data bit (TB8/RB8) for multiprocessor.

  • Mode 3: 9-bit UART, variable baud rate (like Mode 1).

• Comparison: Mode 1 vs Mode 3:

  | Feature | Mode 1 | Mode 3 | | :--- | :--- | :--- | | Data Bits | 8 | 9 | | Baud Rate Source | Timer 1 overflow (variable) | Timer 1 overflow (variable) | | Control Bits | SM2=0, TB8 ignored | SM2 used for multiprocessor, TB8 sent as 9th bit | | Applications | Standard async serial I/O | Multi-processor communication, address/data framing |

• Registers:

  • SBUF: Serial Data Buffer (write for transmit, read for receive).

  • SCON (Serial Control):

    
    SM0 SM1 SM2 REN TB8 RB8 TI RI
    
    

    • SM0,SM1: Mode select (00=Mode0, 01=Mode1, 10=Mode2, 11=Mode3).

    • SM2: Multiprocessor mode enable.

    • REN: Receive enable (1=enable).

    • TB8: Transmit bit 9 (set by software).

    • RB8: Receive bit 9 (stored from 9th bit).

    • TI: Transmit interrupt flag (set after stop bit).

    • RI: Receive interrupt flag (set after stop bit).

• Multiprocessor Communication: When SM2=1 in Mode 2/3, RI is set only if received 9th bit (RB8) is 1. Allows slaves to ignore messages not addressed to them.

I. Interfacing Applications

• ADC Interfacing:

  • Start conversion via control line (e.g., WR pin).

  • Wait for End-of-Conversion (EOC) signal (polling or interrupt).

  • Read converted data via data bus (parallel) or serial shift.

  • Use MOVX instructions to read data from ADC's data register.

• DAC Interfacing:

  • Write digital data to DAC's input latch using MOVX.

  • DAC converts to analog voltage. Timing controlled by write pulse.

  • May need sample-and-hold for stable output.

• Stepper Motor Interfacing:

  • Unipolar (4 or 5 wires) or Bipolar (2-phase).

  • Generate sequence (e.g., full-step: 1010, 1001, 0101, 0110) on two ports.

  • Use delay between steps (timer interrupt or software loop).

  • Driver circuit (ULN2003/ULN2803) provides current sinking/sourcing.

• 8051-based Thyristor Firing Circuit:

  1. Zero Crossing Detection: Use transformer + comparator to detect AC mains zero crossing. Generate interrupt or pulse to 8051.

  2. Firing Angle Control: 8051 timer counts from zero crossing to desired firing angle (e.g., 60° = 3.33ms at 50Hz).

  3. Pulse Generation: When timer overflows, generate a short pulse (via port pin + driver) to trigger thyristor gate.

  4. Accuracy: Use Timer 1 in Mode 1 (16-bit auto-reload) for precise timing. Interrupt-driven for reliable zero-cross detection.

J. RS232 Serial Communication

• RS232 Standard: Logic 1 = -3V to -15V, Logic 0 = +3V to +15V. Uses DB9/DB25 connectors.

• Handshaking Signals:

  • RTS (Request to Send): DTE says "I have data to send".

  • CTS (Clear to Send): DCE says "You may send".

  • DTR (Data Terminal Ready): DTE ready.

  • DSR (Data Set Ready): DCE ready.

  • DCD (Data Carrier Detect): Modem carrier detected.

• Level Conversion: Use MAX232 chip (charge pump) to convert TTL (0-5V) to RS232 levels and vice versa.

• 8051 to RS232 Interfacing:

  • 8051's Txd/Rxd (P3.0/P3.1) → MAX232 → RS232 connector.

  • Handshaking signals (RTS/CTS) can be connected to other port pins if needed.

K. Programming Examples

• Complement Accumulator 900 times:

  
  MOV R2, #900    ; Counter
  
  LOOP: CPL A      ; Complement A
  
  DJNZ R2, LOOP   ; Decrement R2, jump if not zero
  
  

• Four Arithmetic Operations on two 8-bit numbers:

  
  MOV A, #25H     ; First number
  
  MOV B, #10H     ; Second number
  
  ADD A, B        ; A = A + B
  
  MOV R0, A       ; Store sum
  
  MOV A, #25H
  
  SUBB A, B       ; A = A - B (with borrow)
  
  MOV R1, A
  
  MOV A, #25H
  
  MUL AB          ; Product in B:A
  
  MOV R2, B
  
  MOV R3, A
  
  MOV A, #25H
  
  DIV AB          ; Quotient in A, Remainder in B
  
  MOV R4, A
  
  MOV R5, B
  
  

• Lookup Table Operation: Find square of number (0-9) from table.

  
  MOV DPTR, #SQUARE_TABLE
  
  MOV A, #05H     ; Number to square
  
  MOVC A, @A+DPTR ; Get square from table
  
  SJMP $
  
  SQUARE_TABLE: DB 00H, 01H, 04H, 09H, 10H, 19H, 24H, 31H, 40H, 51H
  
  

IV. 8096 MICROCONTROLLER (Medium Frequency)

A. Functional Block Diagram & Hardware Features

• Block Diagram: 16-bit CPU, 232-byte internal RAM (register-mapped), 8-bit/16-bit bus, on-chip peripherals: 10-bit ADC (8 channels), 4 PWM outputs, 3 Timers (16-bit), Serial Port (UART), Watchdog Timer, Interrupt Controller.

• Superiority over 8051:

  • 16-bit data/address bus (vs 8-bit).

  • Higher clock speed (12-16 MHz vs 12 MHz).

  • More on-chip RAM (232 bytes vs 128 bytes).

  • Advanced peripherals (ADC, PWM, more timers).

  • Faster instruction execution (most 1-2 cycles vs 4-12 cycles).

B. Memory Organization

• Memory Map:

  • Internal RAM: 0000H-00E7H (232 bytes). Includes register space (00H-1FH), general RAM (20H-E7H).

  • External Memory: Up to 64KB program (0000H-FFFFH) and 64KB data. Uses multiplexed address/data bus (AD0-AD15).

  • I/O Space: Separate 64KB I/O space, accessed with INS/OUTS instructions.

• Memory Status: 16-bit addressing allows direct access to 64KB memory spaces. Internal RAM is register-mapped for fast access.

C. Instruction Set & Addressing Modes

• Classification: Data Transfer, Arithmetic, Logical, Branch, Control, Interrupt, String, Bit Manipulation.

• Addressing Modes:

  • Immediate: MOV AX, #1234H

  • Direct: MOV AX, [2000H] (16-bit address)

  • Indirect: MOV AX, [BX] (BX holds address)

  • Indexed: MOV AX, [BX+DI] or [BX+SI]

  • Relative: JMP SHORT LABEL (8-bit offset)

• Example Instructions:

  • LDB/STB: Load/Store byte.

  • LDM/STM: Load/Store multiple.

  • PUSH/POP: 16-bit stack operations.

  • DIV/MUL: 16-bit/32-bit operations.

D. Control and Status Registers

• Key Registers:

  • System Configuration Register (SCR): Controls bus width, wait states, chip selects.

  • Interrupt Priority Register (IPR): Sets priority for each interrupt source.

  • Interrupt Mask Register (IMR): Masks individual interrupts.

  • Timer Control Registers (T1CON, T2CON): Mode, gate, enable bits.

  • ADC Control Register (ADCTRL): Start conversion, channel select, mode.

  • PWM Control Registers: Period, duty cycle, enable.

• Function: Configure system operation, enable/disable peripherals, set interrupt priorities, control timing sources.

V. ADVANCED MICROCONTROLLERS (Lower Frequency but Covered)

A. 16-bit PIC Microcontrollers (PIC24/dsPIC33)

• Architecture: Modified Harvard architecture (separate instruction/data buses), 16-bit data path.

• Key Features:

  • RISC instruction set (most instructions single-cycle).

  • Up to 40 MHz operation.

  • Rich I/O (multiple ports, change notification).

  • Advanced timers (16-bit, multiple capture/compare/PWM).

  • Multiple communication modules (UART, SPI, I2C, CAN).

• Applications: Industrial control, motor control, consumer appliances.

B. 32-bit dsPIC Microcontrollers

• Architecture: 16-bit data path with DSP engine (multiply-accumulate unit, barrel shifter).

• Features:

  • High-speed ADC (12-bit, up to 1 MSPS).

  • Multiple PWM outputs with special event triggers.

  • Dedicated DSP instructions for fast signal processing.

  • Up to 40 MIPS.

• Applications: Digital motor control, power supplies, audio processing, industrial automation.

VI. SYSTEM DESIGN & PROGRAMMING METHODOLOGIES

A. Assembly Language Programming Techniques

• Loop Structures:

  • Unconditional: LOOP instruction (uses CX), or DEC reg + JNZ.

  • Conditional: JC/JNC, JZ/JNZ, CMP followed by conditional jump.

• Look-up Tables: Store precomputed values in ROM/EPROM. Use XLAT (8086) or MOVC (8051) with base address in BX/DPTR and index in AL/A.

• Series Processing:

  • Fixed length: Use LOOP or known count.

  • Variable length: Terminate with sentinel value (e.g., 0FFH), check in loop.

• Code Optimization:

  • Use register instructions instead of memory where possible.

  • Use string instructions (REP MOVSB) for block moves.

  • Unroll small loops if speed critical.

  • Choose appropriate addressing mode (register > direct > indirect).

B. Interfacing Design Principles

• Address Decoding:

  • Use decoders (74LS138) to generate chip select (CS) from high-order address lines.

  • Ensure selected peripheral responds only to its address range.

• Bus Buffering/Driving:

  • Use buffers (74LS244/245) for data bus to increase drive capability.

  • Use latches (74LS373/8282) for address bus to hold stable address.

• Timing Considerations:

  • Match peripheral speed to processor.

  • Insert wait states (READY pin in 8086) if peripheral is slow.

  • Check setup/hold times for control signals.

\boxed{\text{This document covers all topics from the approved blueprint based on 5 years of past papers (2022-2025).}}