Microprocessor & Micro‑controller (EX-602) - Unit 1 Short Notes

UNIT 1: Microprocessor & Microcontroller

I. 8086/8088 MICROPROCESSOR

Internal Architecture & Functional Blocks

The 8086 has a two-stage pipelined architecture consisting of:

1. Bus Interface Unit (BIU): Handles all bus operations (address generation, instruction prefetch, read/write).

   • Components: Segment Registers (CS, DS, SS, ES), Instruction Pointer (IP), Address Adder, Instruction Queue (6-byte for 8086, 4-byte for 8088).

   • Role: Fetches instructions and operands from memory, calculates physical addresses.

2. Execution Unit (EU): Executes instructions.

   • Components: ALU, General Purpose Registers (AX, BX, CX, DX), Flag Register, Control Circuit.

   • Role: Decodes and executes instructions, updates flags.

Pipelining: While the EU executes an instruction, the BIU fetches the next instruction(s) into the queue. This overlap improves performance.

Opcode Prefetch Queue: A FIFO buffer in the BIU that stores fetched instruction bytes. The EU reads instructions from this queue, reducing wait states for instruction fetches.

Memory Organization & Segmentation

• 1MB Address Space: $$\displaystyle 2^{20} $$ bytes (00000H to FFFFFH).

• Segmentation: Memory is divided into logical segments. A segment is a contiguous 64KB block.

• Segment Registers: CS (Code), DS (Data), SS (Stack), ES (Extra).

• Physical Address Calculation:

$$ \text{Physical Address} = (\text{Segment Register} \times 10\text{H}) + \text{Offset} $$

The offset is provided by IP, SP, BP, SI, DI, or a displacement.

• Memory Map: Even and odd byte addresses. Word data (2 bytes) is stored with the low-order byte at the lower address (little-endian).

Register Set

FLAGS Register (Key Bits):

• Status Flags: SF (Sign), ZF (Zero), AF (Auxiliary Carry), PF (Parity), CF (Carry), OF (Overflow).

• Control Flags: TF (Trap), IF (Interrupt Enable), DF (Direction for string ops).

Addressing Modes

Stack Structure

• LIFO (Last-In-First-Out) structure in memory.

• Stack Segment (SS) and Stack Pointer (SP) define the top of stack.

• PUSH: Decrements SP by 2 (for word), stores data at SS:SP.

• POP: Reads data from SS:SP, increments SP by 2.

• Word Operations: Stack operations are typically word (16-bit) operations. Byte pushes/pops require SP adjustment.

I/O & Bus Operations

Minimum Mode vs. Maximum Mode:

• Minimum Mode (MN/MX# = 1): Single processor. 8086 generates all bus control signals (RD, WR, ALE, DEN, DT/R, M/IO#).

• Maximum Mode (MN/MX# = 0): Multi-processor system. Bus control signals from external Bus Controller (8288). 8086 outputs status signals (S0, S1, S2) for the 8288 to decode.

Timing Diagrams (Minimum Mode)

A bus cycle consists of T1, T2, T3, T4 states. Wait states (Tw) are inserted between T3 and T4 if READY is low.

• Memory Read Cycle:

  • T1: ALE goes high to latch address. M/IO# = high (memory). DT/R = high (read).

  • T2: ALE goes low. DEN goes active (enables data bus buffer). RD goes low.

  • T3: Data must be valid on bus. If not ready, READY is low → Tw states.

  • T4: RD goes high, data is read by EU. Cycle ends.

• Memory Write Cycle:

  • T1/T2: Similar to read. DT/R = low (write).

  • T3: WR goes low, data is driven onto bus by EU.

  • T4: WR goes high. Cycle ends.

Wait States: Inserted if memory/peripheral is slow. READY signal is sampled at the end of T3. If low, T3 is extended by Tw until READY goes high.

Assembly Language Programming (Applied)

• Data Transfer: MOV, PUSH, POP, XCHG, IN, OUT.

• Arithmetic: ADD, ADC, SUB, SBB, INC, DEC, MUL, IMUL, DIV, IDIV.

• Logical: AND, OR, XOR, NOT, TEST, SHL/SAL, SHR, SAR.

• Branch/Control: JMP, CALL, RET, Jcc (conditional jumps), LOOP.

• String: MOVSB, CMPSB, SCASB, LODSB, STOSB (use REP prefix).

• Example (Series Addition):

  
  MOV CX, 100       ; Count
  
  MOV SI, OFFSET ARRAY
  
  XOR AX, AX        ; Clear sum
  
  CLD               ; Forward direction
  
  NEXT: ADD AL, [SI]
  
  ADC AH, 0         ; Handle carry
  
  INC SI
  
  LOOP NEXT
  
  ; Result in AX
  
  

II. PROGRAMMABLE PERIPHERAL INTERFACE (PPI) - 8255A

Functional Block Diagram

• Data Bus Buffer: 8-bit bidirectional buffer for CPU communication.

• Read/Write Control Logic: Decodes CS, RD, WR signals. Selects ports (A, B, C) or control register.

• Control Register: Stores mode/configuration set by CPU.

• Port A, Port B, Port C: 8-bit I/O ports. Port C can be split into two 4-bit ports for handshaking in Mode 1/2.

Operating Modes

Control Word Format

• Mode Set Flag (D7): 1 = Mode set, 0 = Bit set/reset (for Port C).

• Port A Selection (D6, D5): 00=Mode0, 01=Mode1 input, 10=Mode1 output, 11=Mode2.

• Port C Upper/Lower (D4): 1=Port C upper (PC4-PC7) in Mode 1/2, 0=Port C lower (PC0-PC3) in Mode 1.

• Port B Selection (D3, D2): Similar to Port A (Mode 0/1 only).

• Port C Direction (D1): 1=Output, 0=Input (when Port C in Mode 0).

• Port B Direction (D0): 1=Output, 0=Input.

Example: 10011000B

• D7=1 → Mode Set.

• D6D5=00 → Port A in Mode 0.

• D4=1 → Port C upper in Mode 1/2 (but Port A is Mode 0, so irrelevant).

• D3D2=10 → Port B in Mode 1 Output.

• D1=1 → Port C lower as Output (Mode 0).

• D0=0 → Port B as Input? Wait, D0 is for Port B direction. 0 means Port B is Input? Correction: D0 is Port B direction when Port B in Mode 0. Here Port B is Mode 1, direction is defined by D3D2: 10 = Mode 1 Output. So D0 is don't care for Mode 1. Answer: i) Mode 0, ii) Output (Mode 1 Output), iii) Port C lower as Output (Mode 0), upper as input (default).

Interfacing to 8086

• Connect data bus to D0-D7.

• CS decoded from address lines (e.g., using 3-to-8 decoder).

• RD, WR connected to 8086 bus control signals.

• Ports A, B, C and Control Register assigned different addresses (using A0, A1).

III. PROGRAMMABLE INTERVAL TIMER (PIT) - 8254

Functional Block Diagram

• Data Bus Buffer: 8-bit interface to CPU.

• Read/Write Logic: Decodes CS, RD, WR. Controls access to counters (0,1,2) and control register.

• Control Register: Written by CPU to set mode, select counter, BCD/binary.

• Counters (0,1,2): Each is a 16-bit down counter. Input clock (CLK), Gate (GATE) signal, Output (OUT) signal.

Counter Operation

1. CPU writes a 16-bit count (LSB first) to selected counter.

2. On write of LSB, counter is loaded but held until MSB is written (unless in Mode 0/1/2/3/4? Actually, loading is immediate after LSB write in some modes? Standard: Count is loaded after writing both bytes. For Mode 2/3, writing LSB triggers loading? Clarify: Typically, count is loaded when control word is written or after both bytes are written. Gate must be high to start counting.

3. Counter decrements on each CLK pulse (or CLK/4 in some modes? No, CLK is input clock).

4. When count reaches zero, OUT goes active (mode-dependent). For Mode 0, OUT stays low until reloaded. For Mode 2/3, OUT pulses.

Modes of Operation

Control Word Format

• D7 D6: Select Counter (00=0, 01=1, 10=2, 11=Read-back - optional).

• D5 D4: Read/Write Format: 00=Latch count for reading, 01=Read/Write LSB only, 10=Read/MSB only, 11=Read/Write LSB then MSB.

• D3 D2 D1: Mode (000 to 101 for Modes 0-5).

• D0: BCD (0) or Binary (1).

Applications

• Frequency Generation: Mode 2/3.

• Event Counting: Mode 0 (count external events on CLK).

• Real-Time Clock: Mode 2/3 with known clock frequency.

• Baud Rate Generation: Mode 2 for UARTs (e.g., 8251).

IV. DMA CONTROLLER - 8257

Need for DMA

Direct Memory Access allows peripheral devices to transfer data directly to/from memory without CPU intervention, freeing CPU for other tasks and enabling high-speed transfers (e.g., disk I/O, ADC).

Functional Block Diagram

• 4 Independent Channels (0-3). Each channel has:

  • Current Address Register (CAR): Holds memory address (16-bit, can be auto-incremented/decremented).

  • Current Word Count Register (CWCR): Holds number of words to transfer (16-bit). Decrements on each transfer. When zero, TC (Terminal Count) output goes high.

• Priority Encoder: Resolves simultaneous DREQ requests. Can be Fixed (CH0 > CH1 > CH2 > CH3) or Rotating (programmable via mode set).

• Control Logic: Generates HRQ (Hold Request) to CPU, waits for HLDA (Hold Acknowledge), then controls bus (MEMR, MEMW, IOR, IOW, DACK).

• Mode Set Register: (Optional in basic 8257) Sets priority scheme (fixed/rotate).

Operation Cycle (Burst Mode)

1. Peripheral asserts DREQ (DMA Request) for a channel.

2. 8257 asserts HRQ to CPU.

3. CPU completes current bus cycle, floats buses, asserts HLDA.

4. 8257 takes bus control, asserts DACK for the channel.

5. Transfer: MEMR/MEMW and IOR/IOW active (depending on direction). Address from CAR, data on bus.

6. CAR updated (incremented/decremented), CWCR decremented.

7. If CWCR ≠ 0, repeat step 5. If CWCR = 0, TC for that channel goes high, channel disabled.

8. After last transfer, 8257 negates HRQ. CPU re-acquires bus (HLDA negated).

Control Signals

• HRQ (Output): Hold Request to CPU.

• HLDA (Input): Hold Acknowledge from CPU.

• DREQ0-3 (Input): DMA Request from peripherals.

• DACK0-3 (Output): DMA Acknowledge to peripherals.

• MEMR, MEMW (Output): Memory Read/Write.

• IOR, IOW (Output): I/O Read/Write (for peripheral data register access).

• EOP# (Input/Output): End of Process. Can be input to force termination or output when TC occurs.

Applications

• Disk drive controllers (floppy/hard disk).

• High-speed ADC/DAC data capture.

• Memory-to-memory transfer (using channel 0 as source, channel 1 as destination).

• CRT refresh.

V. USART - 8251

Functional Block Diagram

• Transmitter Section: Parallel-to-Serial converter, Shift Register, Parity Generator, Start/Stop Bit Insertion.

• Receiver Section: Serial-to-Parallel converter, Shift Register, Parity Checker, Start/Stop Bit Detection.

• Data Bus Buffer: Interface to CPU data bus.

• Read/Write Control Logic: Decodes CS, RD, WR. Selects internal registers (Data, Status, Command, Mode).

• Modem Control Unit: Handles modem signals (CTS, RTS, DTR, DSR, RI, DCD).

Key Registers

1. Data Buffer (Read/Write): For transmit data (CPU writes) or receive data (CPU reads).

2. Status Register (Read): Contains TxRDY (Transmitter Ready), RxRDY (Receiver Ready), TxEMPTY, PE (Parity Error), OE (Overrun Error), FE (Framing Error).

3. Control Register (Write): Written with Mode Information (Sync/Async, character length, parity, stop bits) and Command Information (Tx Enable, Rx Enable, DTR, RTS, etc.).

4. Mode Register (Write): Actually part of Control Register write sequence. First write sets mode (synchronous/asynchronous, baud rate factor), second write sets command.

Synchronous vs. Asynchronous Modes

Handshaking Signals (Modem Control)

• CTS (Clear To Send): Input from modem. Must be high to transmit.

• RTS (Request To Send): Output to modem. Indicates DTE ready to transmit.

• DTR (Data Terminal Ready): Output to modem. Indicates DTE is powered/ready.

• DSR (Data Set Ready): Input from modem. Indicates modem is ready.

• RI (Ring Indicator): Input from modem. Indicates incoming call.

• DCD (Data Carrier Detect): Input from modem. Indicates carrier detected.

VI. 8051 MICROCONTROLLER

Architecture & Block Diagram

• CPU: 8-bit ALU, Accumulator (A), B register (for MUL/DIV), Program Status Word (PSW).

• On-chip Memory:

  • Program Memory (ROM/EPROM): 4KB (8051), up to 64KB external. EA pin selects internal/external.

  • Data Memory (RAM): 128 bytes (8051), 256 bytes (8052). Upper 128 bytes (if present) are SFRs.

• I/O Ports (P0-P3): 8-bit each, dual function.

  • P0: I/O or multiplexed low address/data bus (for external memory).

  • P1: Pure I/O (no alternate function).

  • P2: I/O or high address bus (for external memory).

  • P3: I/O with alternate functions (RXD, TXD, INT0, INT1, T0, T1, WR, RD).

• Timers/Counters (T0, T1): 16-bit, can be split (Mode 3). Can count internal clock (timer) or external pulses (counter).

• Serial Communication Unit: Full-duplex UART/SIO. Registers: SCON, SBUF.

• Interrupt System: 5 sources, 2 priority levels. Registers: IE (Interrupt Enable), IP (Interrupt Priority).

Memory Organization

• Internal RAM (128/256 bytes):

  • 00-1FH: 32 bytes for 4 register banks (R0-R7). Selected by PSW bits RS1,RS0.

  • 20-2FH: 16 bytes, bit-addressable (128 bits).

  • 30-7FH/FFH: General purpose RAM.

• External Memory: Up to 64KB each for program and data. Accessed using MOVX instructions. P0 and P2 multiplexed for address/data.

• Program Memory: 0000H-FFFFH. EA=1 uses internal (0000H-0FFFH) then external. EA=0 uses only external.

Pin Configuration (Key Pins)

• VCC, GND: Power.

• XTAL1, XTAL2: Crystal oscillator connections.

• RST: Reset input (active high, min 2 machine cycles).

• ALE: Address Latch Enable. Used to latch low byte of address from P0.

• PSEN: Program Store Enable. Read strobe for external program memory.

• EA: External Access. Selects internal/external program memory.

• P0-P3: I/O ports with alternate functions.

Addressing Modes

Instruction Set Overview (Categories)

• Data Transfer: MOV (register, direct, indirect, immediate), MOVC, MOVX, PUSH, POP, XCH, XCHD.

• Arithmetic: ADD, ADDC, SUBB, INC, DEC, MUL, DIV, DA A (Decimal Adjust).

• Logical: ANL, ORL, XRL, CLR, CPL, RL, RLC, RR, RRC.

• Control Transfer: JMP, CALL, RET, RETI, JZ/JNZ, JC/JNC, JB/JNB/JBC, DJNZ, NOP.

• Bit Manipulation: SETB, CLR, CPL, JB, JNB, JBC (bit-oriented).

Interrupt Structure

• Sources (Priority Natural): IE0 (External 0) > TF0 (Timer 0) > IE1 (External 1) > TF1 (Timer 1) > RI/TI (Serial).

• Registers:

  • IE (Interrupt Enable): EA (global enable), EX0, ET0, EX1, ET1, ES.

  • IP (Interrupt Priority): PX0, PT0, PX1, PT1, PS. 1=high priority, 0=low.

• Response Sequence:

  1. CPU completes current instruction.

  2. Hardware clears TF/RI/TI? No, flags remain. CPU generates LCALL to vector address.

  3. I flag cleared (disables further interrupts of same/lower priority).

  4. ISR executed. Must end with RETI (return and restore I flag).

• Priority Rules: High-priority interrupt can interrupt low-priority ISR. Same priority: natural order. IP register sets software priority.

Timers/Counters

• TMOD Register (Timer Mode): Format: GATE C/T M1 M0 for Timer 1 (high nibble) and Timer 0 (low nibble).

  • GATE: 1=Timer run controlled by TRx and INTx pin. 0=only TRx.

  • C/T: 0=Timer (internal clock), 1=Counter (external Tx pin).

  • M1 M0: Mode selection (00=Mode0, 01=Mode1, 10=Mode2, 11=Mode3).

• TCON Register (Timer Control):

  • TF1, TR1, TF0, TR0: Flags and Run bits for Timer 1/0.

  • IE1, IT1, IE0, IT0: External interrupt 1/0 edge/level control and flags.

• Modes:

  • Mode 0: 13-bit timer (THx:8 bits, TLx:5 bits).

  • Mode 1: 16-bit timer (THx, TLx full).

  • Mode 2: 8-bit auto-reload. TLx counts, reloads from THx on overflow. Good for baud rate.

  • Mode 3: Timer 0 split into two 8-bit timers (TH0, TL0 independent). Timer 1 stops (can be used as baud rate generator if TR1 set).

Serial Communication

• SCON Register (Serial Control):

  • SM0 SM1: Mode select (00=Mode0, 01=Mode1, 10=Mode2, 11=Mode3).

  • SM2: Multiprocessor mode enable (Modes 2/3).

  • REN: Receiver enable.

  • TB8: 9th bit for transmission (Modes 2/3).

  • RB8: 9th bit received (Modes 2/3).

  • TI: Transmit Interrupt flag (set after stop bit, cleared by software).

  • RI: Receive Interrupt flag (set after stop bit, cleared by software).

• Modes:

  • Mode 0: Synchronous, 8-bit, fixed baud = Fosc/12.

  • Mode 1: Asynchronous, 10-bit (1 start, 8 data, 1 stop), variable baud from Timer 1 overflow.

  • Mode 2: Asynchronous, 11-bit (1 start, 9 data, 1 stop), fixed baud = Fosc/64 or Fosc/32 (depends on SMOD in PCON).

  • Mode 3: Asynchronous, 11-bit, variable baud (like Mode 1).

• Baud Rate (Modes 1 & 3):

$$ \text{Baud Rate} = \frac{2^{\text{SMOD}}}{32} \times \frac{\text{Timer 1 Overflow Rate}}{1} $$

For Timer 1 in Mode 2 (auto-reload):

$$ \text{Timer 1 Overflow Rate} = \frac{\text{Fosc}}{12 \times (256 - \text{TH1})} $$

So,

$$ \text{Baud Rate} = \frac{2^{\text{SMOD}}}{32} \times \frac{\text{Fosc}}{12 \times (256 - \text{TH1})} $$

`SMOD` is bit 7 of `PCON` (Power Control register).

Interfacing Applications

• ADC Interfacing:

  • Need: Convert analog sensor signals to digital.

  • Interface: Parallel (e.g., ADC0804) using port pins. Control signals: START (pulse to begin conversion), EOC (End of Conversion, input to 8051), ALE (optional), OE (Output Enable). Read data via MOVX from ADC data pins.

  • Sequence: Pulse START → wait for EOC high → enable output (OE low) → read data.

• DAC Interfacing:

  • Need: Convert digital to analog (e.g., waveform generation).

  • Interface: Parallel (e.g., DAC0800) using port pins. Control: CS (Chip Select), WR (Write strobe). Data latched on WR falling edge.

  • Sequence: Output digital value to port → pulse WR (or use MOVX with WR automatically controlled if memory-mapped).

• RS-232 Interfacing:

  • Need: Convert TTL (0-5V) to RS-232 levels (±3 to ±15V) for serial communication.

  • Interface: Use MAX232 level shifter chip. Connect 8051 TXD to MAX232 T1IN, RXD to R1OUT. Connect MAX232 T1OUT to PC's RXD, R1IN to PC's TXD. Handshaking signals (RTS/CTS) can be connected via additional MAX232 channels.

• Stepper Motor Interfacing:

  • Motor: Unipolar (5/6 wire) or Bipolar (4 wire). Requires sequence of pulses on coils.

  • Drive Circuit: Use ULN2003 (Darlington array) or L293D (H-bridge) to provide sufficient current.

  • 8051: Connect port pins to ULN2003 inputs. Generate step sequence (e.g., full-step: 1010, 0110, 0101, 1001) with delays between steps (using Timer).

• Thyristor Firing Circuit (AC Power Control):

  • Need: Control power to AC loads (lamp, motor) by varying firing angle.

  • Circuit:

    1. Zero-Crossing Detection: Use opto-coupler (e.g., MOC3041) with resistor divider to detect AC zero-crossing. Output pulses at each zero-crossing.

    2. Firing Pulse Generation: 8051 Timer generates delay after each zero-crossing pulse. Delay = firing angle (e.g., 0° to 180°).

    3. Pulse Generation: After delay, another opto-coupler (e.g., MOC3041) triggers the thyristor (SCR/TRIAC) gate.

    4. Isolation: Both opto-couplers provide electrical isolation between 8051 and high-voltage AC side.

  • Accurate Timing: Use Timer in Mode 1 (16-bit) with known clock. Calculate delay count = (firing angle / 360°) × (1/(50Hz/2))? Actually, period of 50Hz is 20ms. Half-cycle = 10ms. Firing angle α (0-180°) corresponds to delay t = (α/180) × 10ms. Timer count = t / (12/Fosc). Use interrupt on zero-crossing for precise synchronization.

VII. 8096/8098 MICROCONTROLLER

Functional Block Diagram

• CPU: 16-bit data path, 8-bit/16-bit bus. 16-bit registers (W0-W15, but banked).

• Memory: 64KB program, 64KB data. External bus multiplexed (address/data on same pins).

• I/O Ports: 8-bit ports (P0-P5), some with alternate functions.

• Timer/Counters: Timer1 (16-bit), Timer2 (16-bit). Can be PWM, capture, compare.

• A/D Converter: 10-bit (or 12-bit), 8/16 channels. Successive approximation.

• Serial Interface: Synchronous (SPI-like) or asynchronous (UART).

• Interrupt System: Multiple sources, maskable/non-maskable, priority levels.

• Watchdog Timer: For system recovery.

• Special Function Registers (SFRs): Memory-mapped registers in upper data memory (FF00H-FFFFH) for control/status.

Hardware Features (Superiority over 8051)

• 16-bit Architecture: Higher performance, larger data handling.

• True 16-bit Data Path: ALU, registers, bus.

• Rich On-Chip Peripherals: ADC (8-16 channels), PWM outputs, multiple timers with capture/compare, serial port (both sync/async), watchdog.

• Banked Registers: Fast context switching for interrupts.

• Higher Speed: Up to 16-20 MHz (vs 12MHz for 8051).

• More I/O Pins: Up to 40+ pins.

Memory Organization

• Program Memory: 0000H-FFFFH (64KB). Can be internal ROM/EPROM or external.

• Data Memory: 0000H-FFFFH (64KB). Lower 256 bytes (00H-FFH) are register banks (16 banks of 8 registers each, R0-R7). Upper memory (100H-FFEFH) is general RAM. SFRs at FF00H-FFFFH.

• External Bus: Multiplexed address/data on AD0-AD15. ALE latches address.

Register Set

• General Purpose Registers (W0-W15): 16-bit, but banked. Only one bank (8 registers) visible at a time via WS (Window Select) bits in PSW. Allows fast interrupt context save.

• Special Function Registers (SFRs): Memory-mapped in upper data space. Key SFRs:

  • IMR (Interrupt Mask Register): Mask individual interrupts.

  • INT_MASK, INT_PEND: Interrupt mask and pending (in some versions).

  • T1CON, T2CON: Timer 1/2 control (mode, gate, count enable).

  • AD_COMMAND, AD_RESULT: ADC control and result.

  • PWM_CONTROL: PWM configuration.

  • PORTx_DATA, PORTx_DIR: Port data and direction.

  • PSW (Program Status Word): Contains WS (Window Select), C (Carry), Z, N (Negative), V (Overflow), etc.

Instruction Set Overview

• Classification: Data Transfer (MOV, PUSH, POP, LDB, STB), Arithmetic (ADD, SUB, MUL, DIV), Logical (AND, OR, XOR, NOT), Bit Manipulation (BITSET, BITCLR, JBC), Program Control (JMP, CALL, RET, Jcc), Interrupt Control (EI, DI, RETI).

• Addressing Modes:

  • Immediate: MOV W0, #1234H

  • Direct: MOV W0, [2000H] (16-bit direct address)

  • Indirect Register: MOV W0, [W1] (W1 holds address)

  • Indirect Memory: MOV W0, [W1++] (post-increment)

  • Relative: JBC W0.3, LABEL (bit test relative)

  • Immediate Short: ADD W0, #10 (short immediate)

  • Indexed: MOV W0, [W1+W2] (base+index)

• Examples:

  • MOV W0, [W1] ; Indirect register.

  • LDB W0, [2000H] ; Load byte from direct address.

  • JBS W0.5, LABEL ; Jump if bit 5 set.

Control & Status Registers

• Interrupt System: IMR masks interrupts. INT_PEND shows pending interrupts. Priority levels (usually 3-4 levels). Non-maskable interrupt (NMI) also available.

• Timer Control: T1CON/T2CON bits: EN (enable), T1S (stop in idle), T1M (mode bits), T1CLK (clock source), T1GATE (gate control). For PWM, additional bits for polarity, period, compare.

• A/D Control: AD_COMMAND: start conversion, select channel, mode (single/continuous), AD_RESULT: read-only conversion result.

• Port Configuration: PORTx_DIR sets direction (0=input, 1=output). PORTx_DATA reads/writes pin state.

VIII. ADVANCED MICROCONTROLLERS

16-bit PIC Microcontrollers (PIC24, dsPIC30/33)

• Architecture: Modified Harvard (separate program/data buses), 16-bit data path, 24-bit instruction word.

• Key Features: High performance (up to 40 MIPS), rich peripherals (ADC up to 1 Msps, DAC, multiple PWM, CAN, USB, Ethernet), low power, C-friendly instruction set (only ~75 instructions), extensive development tools (MPLAB X, XC16 compiler).

• Applications: Industrial control, motor control, consumer appliances, medical devices.

32-bit PIC32 (ARM Cortex-M based)

• Overview: MIPS M4K core (PIC32MX) or ARM Cortex-M4/M7 (PIC32MZ). 32-bit data/address.

• Features: Very high speed (up to 200 MHz), large memory (Flash up to 2MB, RAM up to 512KB), advanced connectivity (Ethernet, USB OTG, CAN, audio), FPU (in M4/M7), DSP instructions.

• Applications: High-performance embedded, networking, audio/video, complex user interfaces.

dsPIC (Digital Signal Processor + Microcontroller)

• Specialization: Combines DSP features (MAC unit, barrel shifter, single-cycle multiply-accumulate, zero-overhead looping) with MCU features (interrupts, I/O, timers).

• Architecture: 16-bit data path, 24-bit instruction word. Modified Harvard with dual data memory reads per cycle.

• Key Peripherals: High-speed ADC (up to 12-bit, 1 Msps), PWM with special features (dead-time control), motor control PWM, audio CODEC interface.

• Applications: Motor control (ACIM, BLDC, PMSM), digital power supplies, audio processing, speech recognition, industrial automation.

IX. COMPARATIVE & CONCEPTUAL TOPICS

Memory-Mapped I/O vs. Isolated (I/O-Mapped) I/O

Minimum Mode vs. Maximum Mode of 8086

Synchronous vs. Asynchronous Serial Communication

Handshaking in I/O

• Without Handshaking: Simple READ/WRITE. CPU must wait for device ready (polling or fixed delays). Risk of data loss if device not ready.

• With Handshaking: Uses control signals to coordinate.

  • Output Handshaking (CPU → Device): CPU places data → asserts STB (Strobe) → device reads data → device asserts IBF (Input Buffer Full) → CPU waits for IBF low before next write.

  • Input Handshaking (Device → CPU): Device places data → asserts OBF (Output Buffer Full) → CPU reads data → CPU asserts ACK (or reads clears OBF) → device waits for ACK before new data.

  • Full Handshaking: Both STB/IBF and OBF/ACK used. 8255 Mode 1 provides this.

Interrupt Priority Handling

• 8051: Natural priority (IE0 > TF0 > IE1 > TF1 > RI/TI). Software priority via IP register. High-priority can interrupt low-priority ISR. Same level: natural order.

• 8257 DMA: Fixed priority (CH0 > CH1 > CH2 > CH3) or Rotating (programmable). Highest priority request gets bus first.

• 8096: Multiple priority levels (typically 3-4). Maskable interrupts via IMR. Non-maskable (NMI) highest. Priority encoded in hardware/software.

• General: Priority Encoder resolves simultaneous requests. Interrupt Nesting allowed if higher priority interrupt arrives during ISR of lower priority.

> [!TIP] EXAM FOCUS

• 8086: Physical address calculation, prefetch queue, timing diagrams (T-states, wait states), memory segmentation, addressing modes, minimum vs maximum mode.

• 8255: Control word interpretation (e.g., 10011000B), Mode 0 vs Mode 1 differences, Port C usage in Mode 1.

• 8254: Mode 2 (rate generator) and Mode 3 (square wave) are most common. Control word format.

• 8257: DMA cycle (HRQ/HLDA handshake), registers per channel, priority schemes.

• 8051: TMOD/TCON bits, SCON bits, baud rate formula (Mode 1/3), interrupt vector addresses, memory map (internal RAM banks, SFRs), addressing modes (especially @DPTR, @Ri), thyristor firing circuit (zero-crossing + delay).

• 8096: Contrast with 8051 (16-bit, banked registers, SFRs at FF00H-FFFFH), key SFRs (IMR, T1CON, AD_COMMAND), addressing modes (indexed [W1+W2]).

• Comparative: Memory-mapped vs I/O-mapped, synchronous vs async serial, 8086 min/max mode, handshaking signals.

> [!CAUTION] COMMON PITFALLS

• 8086: Confusing offset with physical address. Forgetting segment register must be loaded before using [ ] with displacement. Misinterpreting M/IO# in max mode (it's not present; use S0-S2).

• 8255: Port C in Mode 1 is split; upper/lower halves used for handshaking. Control word bit D4 determines which half is used for handshaking when Port A/B in Mode 1.

• 8254: Mode 2 and 3 both generate periodic waves, but Mode 3 has ~50% duty cycle. Mode 0 is one-shot.

• 8051: MOV A, @A+DPTR is indexed addressing (for lookup tables), not direct/indirect. PUSH/POP use direct addressing (only internal RAM, not SFRs). EA pin: 1 = internal then external, 0 = external only.

• Baud Rate: For 8051, baud rate depends on SMOD (PCON.7) and Timer 1 reload value (TH1). SMOD=1 doubles baud.

• 8096: Registers are banked (W0-W7 visible at a time). WS bits in PSW select window. SFRs are in upper data memory (FF00H-FFFFH), not lower.

• Thyristor Firing: Zero-crossing detection provides reference. Firing angle delay measured from zero-crossing, not from previous pulse. Use interrupt on zero-crossing for accuracy.