Analog Electronics (EX-305) - Unit 3 Short Notes

UNIT 3: Analog Electronics Short Notes

(Based on RGPV Past Papers: Dec 2024, Jun 2024, Dec 2023, Jun 2023)

1. Semiconductor Diodes

P-N Junction Diode

• Structure: P-type and N-type semiconductors joined → forms depletion region with built-in potential \(V_{bi}\).

• V-I Characteristics:

  • Forward bias: Exponential rise after cut-in voltage (\(V_\gamma\) ≈ 0.7V Si, 0.3V Ge).

    \[ I = I_S \left( e^{\frac{V}{\eta V_T}} - 1 \right), \quad V_T = \frac{kT}{q} \approx 26\,\text{mV at 300K} \]

  • Reverse bias: Small reverse saturation current \(I_S\) (µA).

• Working Principle:

  • Forward bias → depletion width ↓ → carriers cross junction → current flows.

  • Reverse bias → depletion width ↑ → high resistance.

  • Energy band diagram: Forward bias lowers barrier, reverse bias raises barrier.

• Breakdown Mechanisms:

  • Zener breakdown (\(V_Z < 5\,\text{V}\)): Tunneling due to high electric field.

  • Avalanche breakdown (\(V_Z > 7\,\text{V}\)): Carrier multiplication via collision.

• Applications: Rectification, switching, voltage regulation (Zener), protection (TVS), frequency mixing.

[!TIP]

Exam Focus: Derive diode current equation, explain breakdown mechanisms, sketch V-I curve with labels.

Special Purpose Diodes

[!TIP]

Short Notes: Tunnel diode (negative resistance), Varactor (C-V relation), LED (materials: GaAs, GaP).

2. Diode-Based Waveform Circuits

Rectifiers

• Half-Wave Rectifier:

  • Circuit: Diode + load \(R_L\).

  • Output: \(V_o = V_m \sin \omega t\) for \(0 \le \omega t \le \pi\), 0 otherwise.

  • Efficiency \(\eta = \frac{P_{DC}}{P_{AC}} = \frac{40.6\%}{}\) (max).

  • Ripple factor \(r = \frac{V_{r(rms)}}{V_{DC}} = 1.21\) (no filter).

• Full-Wave Rectifiers:

  • Center-tapped: Two diodes, center-tapped transformer.

  • Bridge: Four diodes, no center tap.

  • Efficiency \(\eta_{\text{max}} = 81.2\%\).

  • Ripple factor (capacitor filter): \(r = \frac{1}{4\sqrt{3} f R_L C}\) (full-wave).

• Voltage Multipliers:

  • Doubler, tripler, quadrupler → cascaded capacitor-diode networks.

  • Applications: CRTs, high-voltage supplies.

[!TIP]

Derive Efficiency: Show \(P_{DC} = \frac{V_m^2}{2R_L}\) for full-wave, \(P_{AC} = \frac{V_m^2}{R_L}\) → \(\eta = 81.2\%\).

Filters

• Capacitor Input (π-filter): Capacitor after rectifier → reduces ripple by charging/discharging.

• Choke Input (L-type): Inductor in series → smooths current; ripple factor \(r = \frac{R_L}{2\sqrt{2} f L}\) (full-wave).

• LC Filter: L and C in π-configuration → better ripple rejection; design for 1% ripple: \(\frac{1}{\sqrt{2} f^2 L C} = 0.01\).

Clippers

• Single-ended: Clips positive/negative half-cycles.

  • Example: Diode + battery → shift clipping level.

• Double-ended: Clips both halves; equal amplitude → symmetrical clipping; unequal → asymmetric.

• Biased Clippers: Add DC bias to set clipping threshold.

Clampers

• Positive/Negative Clampers: Shift entire waveform to +ve/-ve side using capacitor and diode.

• Biased Clampers: Add DC bias to set clamping level.

• Clamping Theorem:

  \[ V_{\text{out}} = V_{\text{in}} + V_{\text{clamp}} \quad \text{(output follows input with offset)} \]

  • Waveform restoration after clipping.

[!TIP]

Waveform Analysis: Draw input/output for sinusoidal and square waves; mark clamping voltage.

3. Bipolar Junction Transistors (BJTs)

Structure & Types

• NPN vs PNP:

  | Feature | NPN | PNP | |---------------|------------------------------|------------------------------| | Symbol | Arrow out (emitter) | Arrow in | | Current | Electrons majority | Holes majority | | Biasing | \(V_C > V_B > V_E\) | \(V_E > V_B > V_C\) | | Switching | Faster (electron mobility) | Slower |

• Transistor Action:

  • Emitter injection: Heavy doping → injects carriers.

  • Transport: Base narrow → most carriers cross to collector.

  • Collection: Reverse-biased collector-base junction sweeps carriers.

Operating Regions

Configurations

Parameters

• \(\alpha\) and \(\beta\):

  \[ \alpha = \frac{I_C}{I_E}, \quad \beta = \frac{I_C}{I_B}, \quad \alpha = \frac{\beta}{\beta+1} \]

• h-parameters (hybrid):

  \[ h_{11} = \left. \frac{\Delta V_{BE}}{\Delta I_B} \right|_{V_{CE}=\text{const}} \quad (\text{input impedance}) \]

  \[ h_{12} = \left. \frac{\Delta V_{BE}}{\Delta V_{CE}} \right|_{I_B=\text{const}} \quad (\text{reverse voltage gain}) \]

  \[ h_{21} = \left. \frac{\Delta I_C}{\Delta I_B} \right|_{V_{CE}=\text{const}} = \beta \]

  \[ h_{22} = \left. \frac{\Delta I_C}{\Delta V_{CE}} \right|_{I_B=\text{const}} = \frac{1}{r_o} \]

Biasing Techniques

• Fixed Bias:

  \[ I_B = \frac{V_{CC} - V_{BE}}{R_B}, \quad I_C = \beta I_B \]

  Stability factor \(S = 1 + \beta\) → poor thermal stability.

• Self-Bias (Emitter Bias):

  • \(R_B\) from base to \(V_{CC}\), \(R_E\) in emitter.

  • Design: Given \(I_C\), \(V_{CE}\), find \(R_B\), \(R_C\), \(R_E\).

  • Stability factor \(S \approx 1 + \frac{R_B}{R_E}\) (for large \(\beta\)).

• Voltage Divider Bias:

  • \(R_1\), \(R_2\) form divider → stable \(V_B\).

  • \(I_E \approx \frac{V_B - V_{BE}}{R_E}\), \(I_C \approx I_E\).

  • Stability factor \(S = \frac{(1+\beta)(R_B + R_E)}{R_E + (1+\beta)R_B} \approx 1 + \frac{R_B}{R_E}\) if \(R_B = R_1 \parallel R_2\).

• Thermal Runaway: \(\uparrow T \rightarrow \uparrow I_C \rightarrow \uparrow P_C \rightarrow \uparrow T\) → destructive.

  Solution: Use emitter resistor \(R_E\) for negative feedback.

Load Line Analysis

• DC Load Line:

  \[ I_C = \frac{V_{CC} - V_{CE}}{R_C} \]

  • Cut-off: \(I_C = 0\), \(V_{CE} = V_{CC}\).

  • Saturation: \(V_{CE} \approx 0\), \(I_C = \frac{V_{CC}}{R_C}\).

  • Q-point: Intersection of load line and transistor characteristic.

• AC Load Line: Uses dynamic resistance \(r_e = \frac{25\,\text{mV}}{I_E}\) and AC load \(R_{L,ac}\).

  • Maximum swing: Q-point centered between saturation and cut-off.

Small-Signal Analysis

• Hybrid-π model:

  \[ v_{be} = i_b r_{\pi}, \quad i_c = \beta i_b + g_m v_{be}, \quad g_m = \frac{I_C}{V_T} \]

• h-parameter equivalent:

  \[ v_1 = h_{11} i_1 + h_{12} v_2, \quad i_2 = h_{21} i_1 + h_{22} v_2 \]

• CE Amplifier Gains:

  \[ A_v = -g_m R_{L,ac}, \quad A_i = \beta, \quad A_p = A_v A_i \]

  \[ R_{in} = r_{\pi} \parallel R_B, \quad R_{out} = R_C \parallel r_o \]

Transistor as Amplifier

• Principle: Small \(v_{be}\) → large \(\Delta i_c\) → voltage/current amplification.

• Key: Operate in active region with proper DC biasing.

4. Field Effect Transistors (FETs)

JFET

• Construction:

  • N-channel: N-type channel, P-type gate.

  • P-channel: P-type channel, N-type gate.

• Working: Reverse-biased gate-channel junction → depletion region controls channel width.

• Parameters:

  • Pinch-off voltage \(V_P\) (negative for N-channel, positive for P-channel).

  • Saturation current \(I_{DSS}\) (when \(V_{GS}=0\)).

• Shockley’s Equation (saturation region):

  \[ I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2 \quad (V_{GS} > V_P \text{ for N-channel}) \]

• V-I Characteristics:

  • Ohmic region (\(V_{DS}\) small): \(I_D \propto V_{DS}\) → resistor.

  • Saturation (\(V_{DS} \ge V_{GS} - V_P\)): \(I_D\) constant.

  • Cut-off (\(V_{GS} \le V_P\)): \(I_D \approx 0\).

• Self-Bias Design (N-channel):

  Given \(V_P\), \(I_{DSS}\), \(V_{DD}\), find \(R_D\), \(R_S\) for specified \(I_D\), \(V_{DS}\).

  \[ V_{GS} = -I_D R_S, \quad V_{DS} = V_{DD} - I_D (R_D + R_S) \]

  Solve from Shockley and \(V_{DS}\) equation.

[!EXAMPLE]

Jun 2024: P-channel JFET, \(V_P = -5\,\text{V}\), \(I_{DSS}=12\,\text{mA}\), \(V_{DD}=12\,\text{V}\), \(I_D=5\,\text{mA}\), \(V_{DS}=6\,\text{V}\).

Solution:

\[ > I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2 \Rightarrow 0.005 = 0.012 \left(1 - \frac{V_{GS}}{-5}\right)^2 > \]

\[ > \Rightarrow 1 + \frac{V_{GS}}{5} = \sqrt{\frac{5}{12}} \approx 0.6455 \Rightarrow V_{GS} = -1.7725\,\text{V} > \]

For self-bias (source to \(V_{DD}\) via \(R_S\), gate grounded):

\[ > V_{GS} = -V_{DD} + I_D R_S \Rightarrow -1.7725 = -12 + 0.005 R_S \Rightarrow R_S = 2045.5\,\Omega > \]

\[ > |V_{DS}| = V_{DD} - I_D(R_D+R_S) = 6 \Rightarrow 12 - 0.005(R_D+2045.5)=6 \Rightarrow R_D = -845.5\,\Omega > \]

Note: Negative \(R_D\) indicates given conditions not feasible with this circuit. In practice, adjust \(I_D\) or \(V_{DS}\).

MOSFET

• Enhancement Mode: No channel initially; requires \(V_{GS} > V_{th}\) to create channel.

• Depletion Mode: Channel exists at \(V_{GS}=0\); \(V_{GS}\) depletes channel.

• Four Elements: Gate (G), Source (S), Drain (D), Substrate (B).

• CMOS: Complementary MOSFETs (N + P) → low static power, high noise immunity. Used in digital ICs.

FET vs BJT

5. Transistor Amplifiers & Power Stages

Small-Signal Amplifiers

• CE: High voltage gain, phase reversal, moderate input impedance.

• CB: Low input impedance, no phase reversal, high-frequency use.

• CC: Voltage follower, high input impedance, low output impedance.

Power Amplifiers

• Class A:

  • Q-point at center of load line.

  • Efficiency \(\eta_{\text{max}} = 50\%\).

  • Distortion low, power dissipation high.

• Class B:

  • Q-point at cut-off → two transistors in push-pull.

  • Efficiency \(\eta_{\text{max}} = 78.5\%\).

  • Crossover distortion near zero crossing.

  • Design:

    \[ P_o = \frac{V_{\text{peak}}^2}{2 R_L}, \quad P_{DC} = \frac{2 V_{CC} V_{\text{peak}}}{\pi R_L}, \quad \eta = \frac{\pi V_{\text{peak}}}{4 V_{CC}} \]

    For \(V_{\text{peak}} = V_{CC}\), \(\eta = 78.5\%\).

• Class AB: Compromise between A and B → reduced crossover distortion.

• Class C: Conduction < 180° → high efficiency, used in RF.

[!EXAMPLE]

Jun 2023: Class B, \(V_{CC}=24\,\text{V}\), \(R_L=8\,\Omega\), \(V_{\text{p-p}}=22\,\text{V}\).

\[ > V_{\text{peak}} = 11\,\text{V}, \quad P_o = \frac{11^2}{2 \times 8} = 7.5625\,\text{W} > \]

\[ > I_{\text{peak}} = \frac{11}{8} = 1.375\,\text{A}, \quad I_{\text{avg}} = \frac{2 I_{\text{peak}}}{\pi} = 0.8755\,\text{A} > \]

\[ > P_{DC} = 24 \times 0.8755 = 21.012\,\text{W}, \quad \eta = \frac{7.5625}{21.012} \times 100\% = 35.99\% > \]

Darlington Pair

• Circuit: Two BJTs connected → emitter of first to base of second.

• Current gain: \(\beta_{\text{total}} \approx \beta_1 \beta_2\) (very high).

• Input impedance: \(h_{ie1} + \beta_1 (h_{ie2} + R_{E2})\) → very high.

• Applications: Driver stages, impedance matching, current sources.

6. Differential Amplifiers

Basic Differential Pair

• Circuit: Two matched transistors with common emitter resistor \(R_E\) (or current source) and collector loads \(R_C\).

• Operation:

  • Differential mode: \(v_{i1} = -v_{i2}\) → outputs opposite.

  • Common mode: \(v_{i1} = v_{i2}\) → outputs same (ideally rejected).

Key Parameters

• Differential voltage gain \(A_d = \frac{v_{od}}{v_{id}} = -g_m R_C\) (single-ended output).

• Common-mode gain \(A_c = \frac{v_{oc}}{v_{ic}} \approx -\frac{R_C}{2R_E}\) (with resistive \(R_E\)).

• CMRR (Common-Mode Rejection Ratio):

  \[ \text{CMRR} = \left| \frac{A_d}{A_c} \right|, \quad \text{CMRR}_{\text{dB}} = 20 \log \left| \frac{A_d}{A_c} \right| \]

  High CMRR → good noise rejection.

• With active load (current mirror): \(A_d\) doubles, \(A_c \approx 0\) → CMRR very high.

[!EXAMPLE]

Dec 2024: \(A_d = 100\), \(A_c = 0.1\) → \(\text{CMRR} = 1000\) or \(60\,\text{dB}\).

Applications

• Input stage of op-amps, instrumentation amplifiers, noise rejection in balanced lines.

7. Feedback Amplifiers

Feedback Concepts

• Positive feedback: Reinforces input → oscillations (used in oscillators).

• Negative feedback: Opposes input → stabilizes gain, reduces distortion.

• Topologies:

  • Voltage-series (voltage amplifier): Sample voltage, series mix.

  • Voltage-shunt (transresistance amplifier).

  • Current-series (current amplifier).

  • Current-shunt (transconductance amplifier).

Effects of Negative Feedback

• Gain reduction: \(A_f = \frac{A}{1 + A\beta}\) (for negative feedback).

• Bandwidth increase: Gain-bandwidth product constant → \(BW_f = BW (1 + A\beta)\).

• Distortion/noise reduction: By factor \((1 + A\beta)\).

• Input/output impedance changes:

  • Voltage-series: \(Z_{in} \uparrow\), \(Z_{out} \downarrow\).

  • Current-series: \(Z_{in} \uparrow\), \(Z_{out} \uparrow\).

• Stability: Avoid oscillations by ensuring \(|A\beta| < 1\) at phase shift = 180°.

8. Oscillators

Barkhausen Criterion

• Conditions for sustained oscillations:

  1. \(|A\beta| = 1\) (loop gain magnitude unity).

  2. Phase shift around loop = \(0^\circ\) (or \(360^\circ\)).

RC Oscillators

• RC Phase-Shift Oscillator:

  • Circuit: Three RC networks in feedback (60° each) + amplifier (180°).

  • Frequency:

    \[ f = \frac{1}{2\pi RC\sqrt{6}} \quad (\text{for three sections}) \]

• Wein Bridge Oscillator:

  • Circuit: Series-parallel RC network + non-inverting amplifier.

  • Frequency:

    \[ f = \frac{1}{2\pi RC} \]

  • Design: For \(f = 2\,\text{MHz}\), choose \(R\) and \(C\) such that \(RC = \frac{1}{2\pi \times 2 \times 10^6} \approx 79.6\,\text{ns}\).

LC Oscillators

• Hartley Oscillator:

  • Circuit: Split inductor (\(L_1\), \(L_2\)) or tapped coil + capacitor \(C\).

  • Frequency:

    \[ f = \frac{1}{2\pi \sqrt{L_{\text{eq}} C}}, \quad L_{\text{eq}} = L_1 + L_2 + 2M \approx L_1 + L_2 \]

• Colpitts Oscillator:

  • Circuit: Split capacitor (\(C_1\), \(C_2\)) + inductor \(L\).

  • Frequency:

    \[ f = \frac{1}{2\pi \sqrt{L C_{\text{eq}}}}, \quad C_{\text{eq}} = \frac{C_1 C_2}{C_1 + C_2} \]

• Comparison: Hartley uses inductive divider, Colpitts uses capacitive divider → Colpitts better for high frequencies.

Crystal Oscillator

• Equivalent Circuit: Series \(R\), \(L\), \(C\) and parallel \(C_p\).

• Resonances:

  • Series resonance \(f_s = \frac{1}{2\pi\sqrt{LC}}\) → low impedance.

  • Parallel resonance \(f_p > f_s\) → high impedance.

• Frequency Stability: Extremely high (Q ≈ 10⁴–10⁶).

• Applications: Clocks, RF transmitters, watches.

• Pierce Configuration: Crystal between amplifier input and ground → common.

9. Multivibrators & 555 Timer

Multivibrators

• Astable: No stable state → continuous oscillation.

  • Frequency (transistor version): \(f \approx \frac{1}{1.4 RC}\) (approx).

• Monostable: One stable, one quasi-stable → one pulse per trigger.

  • Pulse width \(T = 0.69 RC\) (transistor).

• Bistable: Two stable states → flip-flop, memory.

555 Timer IC

• Internal Block: Two comparators, flip-flop, discharge transistor, voltage divider (3× \(V_{CC}\)).

• Astable Mode:

  • Circuit: \(R_A\), \(R_B\), \(C\) between discharge pin and ground.

  • Frequency & Duty Cycle:

    \[ T_1 = 0.693 (R_A + R_B) C, \quad T_2 = 0.693 R_B C \]

    \[ f = \frac{1.44}{(R_A + 2R_B) C}, \quad \text{Duty cycle} = \frac{R_A + R_B}{R_A + 2R_B} \times 100\% \]

• Monostable Mode:

  • Pulse width:

    \[ T = 1.1 R C \]

• Applications: Pulse generation, time delay, waveform generation, PWM.

[!TIP]

Derive Astable Frequency: Use capacitor charging/discharging through \(R_A+R_B\) and \(R_B\).

10. Operational Amplifiers (Op-Amps)

Ideal Op-Amp Characteristics

• Infinite open-loop gain \(A_{OL} \to \infty\).

• Infinite input impedance \(Z_{in} \to \infty\) → no current into inputs.

• Zero output impedance \(Z_{out} = 0\).

• Infinite bandwidth, zero offset voltage.

• Virtual ground: In negative feedback, \(v_+ \approx v_-\) due to high gain.

Practical Op-Amp Limitations

• Finite gain (10⁵–10⁶), input bias current (nA–µA), input offset voltage (mV).

• Slew rate: Max rate of output change (V/µs) → limits bandwidth.

• Gain-bandwidth product: Constant → \(f_{\text{unity}} = A_{OL} \times BW\).

• CMRR, PSRR (power supply rejection ratio).

Basic Configurations

• Inverting Amplifier:

  \[ A_v = -\frac{R_f}{R_{in}}, \quad Z_{in} = R_{in} \]

• Non-Inverting Amplifier:

  \[ A_v = 1 + \frac{R_f}{R_1}, \quad Z_{in} \to \infty \]

• Voltage Follower (Buffer):

  \[ A_v = 1, \quad Z_{in} \text{ very high}, \quad Z_{out} \text{ very low} \]

Special Applications

• Integrator:

  • Circuit: \(R_{in}\) to \((-)\) input, \(C_f\) in feedback.

  • Output: \(v_o = -\frac{1}{R_{in} C_f} \int v_{in} \, dt\).

  • For sine input → cosine output; square input → triangular.

• Differentiator:

  • Circuit: \(C_{in}\) in series, \(R_f\) in feedback.

  • Output: \(v_o = -R_f C_{in} \frac{dv_{in}}{dt}\).

  • Limitation: Amplifies high-frequency noise → add \(R_{in}\) in series with \(C_{in}\).

• Logarithmic Amplifier:

  • Diode in feedback → \(v_o = -\frac{kT}{q} \ln\left(\frac{v_{in}}{I_s R_f}\right)\).

  • Applications: Compression, decibel conversion.

• Zero-Crossing Detector:

  • Comparator with \(v_+ = 0\) → output switches when \(v_-\) crosses zero.

  • Sine input → square output.

• Schmitt Trigger:

  • Hysteresis: \(V_{UT} = V_{ref} \frac{R_1}{R_1+R_2}\), \(V_{LT} = -V_{ref} \frac{R_1}{R_1+R_2}\) (inverting).

  • Applications: Noise immunity, waveform shaping.

11. Active Filters & Advanced Op-Amp Circuits

Active Filters

• Advantages over passive: Gain, no loading, high Q, small size.

• First-Order Low-Pass:

  • Circuit: \(R\) and \(C\) in feedback or input.

  • Cutoff frequency: \(f_c = \frac{1}{2\pi RC}\).

  • Passband gain: \(1 + \frac{R_f}{R_1}\) (non-inverting).

• Second-Order Low-Pass (Sallen-Key):

  • Unity gain: \(f_c = \frac{1}{2\pi\sqrt{R_1 R_2 C_1 C_2}}\).

  • With gain \(A\): \(f_c\) reduces slightly.

  • Design: For given \(f_c\), choose \(R_1=R_2=R\), \(C_1=C_2=C\) → \(f_c = \frac{1}{2\pi RC}\).

  [!EXAMPLE]

  Jun 2023: \(R_1=R_2=33\,\text{k}\Omega\), \(C_1=C_2=0.0047\,\mu\text{F}\), \(R_f=7\,\text{k}\Omega\), \(R=27\,\text{k}\Omega\) (likely input resistor).

  Assuming Sallen-Key with gain:

  \[ > f_c = \frac{1}{2\pi\sqrt{33 \times 10^3 \times 33 \times 10^3 \times 4.7 \times 10^{-9} \times 4.7 \times 10^{-9}}} \approx 324\,\text{Hz} > \]

  Passband gain \(A_v = 1 + \frac{R_f}{R_1} = 1 + \frac{7}{33} \approx 1.212\).

Summing & Difference Amplifiers

• Summing Amplifier (inverting):

  \[ v_o = -R_f \left( \frac{v_1}{R_1} + \frac{v_2}{R_2} + \cdots \right) \]

• Differential Amplifier:

  • Using op-amp with four resistors → \(v_o = \frac{R_f}{R_1}(v_2 - v_1)\) if \(R_1=R_3\), \(R_2=R_4\).

  • CMRR improvement: Use precision matched resistors.

12. Miscellaneous & Short Note Topics

CMOS

• Construction: Complementary pair (N-MOS + P-MOS) in series between \(V_{DD}\) and ground.

• Merits: Near-zero static power, high noise margin, high density.

• Applications: Digital ICs, microprocessors, memory.

LED

• Construction: Direct bandgap semiconductor (GaAs, GaP, GaN).

• Working: Electron-hole recombination → photon emission.

• Efficiency: Quantum efficiency, internal vs external.

• Applications: Displays (7-segment), indicators, traffic lights, optical comms.

Enhancement Mode MOSFET

• Operation: No channel at \(V_{GS}=0\); requires \(V_{GS} > V_{th}\) (N-channel) to induce channel.

• Symbol: Arrow from body to gate for N-channel? Actually, body connected to source for discrete?

• Applications: Digital circuits (CMOS), switches, analog multiplexers.

Crystal Oscillator

• Frequency Stability: Due to high Q of crystal.

• Equivalent Circuit: Series RLC (motional arm) parallel with \(C_p\).

• Pierce Configuration: Crystal between op-amp input and ground → common.

Bistable Multivibrator

• Circuit: Two cross-coupled transistors or op-amp with positive feedback.

• Operation: Two stable states; triggered by external pulse.

• Applications: Flip-flops, memory cells, frequency dividers.

Op-Amps Summary

• Key Parameters:

  • Slew rate (SR): \(\text{SR} = \frac{dV_o}{dt}_{\text{max}}\) (V/µs).

  • CMRR: Rejects common-mode signals.

  • PSRR: Rejects power supply variations.

• Popular ICs:

  • 741: General purpose, 18 pins, SR ≈ 0.5 V/µs.

  • LM324: Quad op-amp, single supply, low power.

END OF UNIT 3
Focus on derivations (efficiency, ripple factor, oscillator frequency), circuit analysis (clippers/clampers, amplifiers), and numerical problems (biasing, CMRR, power amplifiers).