Microcontroller & Embedded system (EC-604 (A)) - Unit 5 Short Notes

UNIT 5: Microcontroller & Embedded Systems

I. Embedded System Fundamentals

Definition and Core Concept

An embedded system is a dedicated computer system designed to perform one or a few specific functions within a larger mechanical or electrical system. It is typically embedded as part of a complete device, often with real-time computing constraints.

Key Differentiation from General-Purpose Computing Systems:

| Aspect | Embedded System | General-Purpose System |

|--------------------------|----------------------------------------------|-----------------------------------------|

| Purpose | Dedicated, specific function | Versatile, multiple applications |

| Design Constraints | Strict (cost, power, size, real-time) | Flexible (performance, user experience)|

| Resource Usage | Optimized, minimal | High (CPU, memory, I/O) |

| Software | Often firmware, rarely changed | General OS, frequent updates |

| User Interaction | Limited or none (headless) | Extensive (GUI, peripherals) |

Characteristics

• Hardware-Software Integration: Tight coupling; software is tailored to specific hardware.

• Real-Time Operation:

  • Hard Real-Time: Missing deadline causes system failure (e.g., airbag control).

  • Soft Real-Time: Missing deadline degrades performance (e.g., video streaming).

• Resource Constraints: Limited power (battery-operated), memory (RAM/ROM), cost, and physical size.

• Reliability & Robustness: Must operate in harsh environments for years without failure.

Quality Attributes

• Performance: Speed, throughput, latency.

• Dependability: Reliability, availability, safety.

• Security: Protection against unauthorized access.

• Modifiability & Portability: Ease of updates and hardware/software reuse.

Design Metrics

• Primary: Cost, performance (MIPS), power consumption (mW), memory footprint (KB), size/weight.

• Secondary: Time-to-market, maintainability, scalability.

Classification of Embedded Systems

Major Application Areas

Consumer electronics (TV, camera), Automotive (engine control, ABS), Industrial (PLC, robotics), Medical (pacemaker, MRI), Telecom (switches, routers), Aerospace (satellite, avionics).

II. Processor Architectures for Embedded Systems

Types of Processors

Memory Architecture

• Von Neumann: Single memory for code & data. Simpler, but bottleneck (fetch/decode/execute cannot overlap). Used in many GPPs (x86).

• Harvard: Separate memories/ buses for code & data. Allows simultaneous access, faster, avoids contention. Common in microcontrollers (8051, PIC).

Suitability: Harvard preferred for embedded due to deterministic timing and speed.

Instruction Set Architecture (ISA)

Specialized Processors

ARM Processor Family

• RISC Features: Load/store architecture (memory access only via load/store instructions), fixed 32-bit (ARM) or 16-bit (Thumb) instructions, large register file (16 registers), pipelined execution.

• Use in Mobile: Dominant due to power efficiency (low power modes), performance per watt, and vast ecosystem (tools, OS support like Android/Linux).

DSP Processors

• Special Features: Hardware multiplier/accumulator (MAC), pipelining, zero-overhead looping, dedicated address generation units (circular buffers), Harvard memory.

• Role vs GPP: Optimized for mathematical intensity (filters, transforms). GPPs handle control tasks; DSPs handle signal processing with higher throughput and lower power for same task.

III. 8051 Microcontroller

Timer/Counter Operations

Example: 1 kHz Square Wave at P2.3 (Timer 0, Mode 1, 11.0592 MHz Crystal)

• Timer clock = Crystal/12 = 11.0592 MHz / 12 = 921.6 kHz

• Timer tick = 1 / 921.6 kHz ≈ 1.085 µs

• For 1 kHz square wave, period = 1 ms, half-period = 0.5 ms.

• Number of ticks for 0.5 ms = 0.5 ms / 1.085 µs ≈ 461 ticks.

• 16-bit max = 65536. Reload value = 65536 - 461 = 65075 = 0xFE3B.

• TH0 = 0xFE, TL0 = 0x3B. Toggle P2.3 in interrupt.

Serial Communication (Modes 0–3)

Comparison: Mode 1 vs Mode 3

• Similarity: Both are asynchronous, start+stop bits, variable baud from Timer 1.

• Difference: Mode 1 is 8-bit data; Mode 3 is 9-bit (9th bit programmable for address/data).

• Application: Mode 1 for simple point-to-point; Mode 3 for multi-processor systems where 9th bit identifies address frame.

Interfacing

DAC Interfacing

• Circuit: Parallel data lines (P1) to DAC input, control signals (CS, WR), analog output filtered.

• Timing: Write data to port → pulse WR low → DAC converts → analog output stable.

• Software: Load data to port, toggle WR pin.

• Applications: Waveform generation (sine, square), analog control (motor speed), audio.

ADC Interfacing

• Circuit: Analog input → ADC (e.g., 0808), control (CS, WR, RD), data bus to port.

• Steps: Select channel (address lines), start conversion (WR pulse), wait for EOC, read data (RD pulse).

• Start/Read: WR starts conversion; RD enables output buffers.

Stepper Motor Interfacing

• Driver: ULN2003 (Darlington array) or L293D (H-bridge).

• Sequence: Full-step (1-2-3-4) or half-step (1-1.5-2-2.5...). Pulse sequence on control pins.

• Control Program: Delay between steps determines speed.

Data Acquisition System (8051-based)

Block Diagram: Sensor → Signal Conditioning (amplifier/filter) → ADC → 8051 (process/store) → Output (LCD/PC/actuator). Signal Flow: Analog signal → conditioned → digitized → processed → decision/display/control.

Serial Port Programming in Embedded C (Mode 1, Polling)

#include <reg51.h>

void serial_init() {

    SCON = 0x50; // Mode 1, 8-bit UART, enable receiver

    TMOD = 0x20; // Timer 1, Mode 2 (auto-reload)

    TH1 = 0xFD;  // 9600 baud @ 11.0592 MHz

    TR1 = 1;     // Start Timer 1

    TI = 1;      // Ready to transmit

}
void serial_tx(char c) {

    SBUF = c;

    while (!TI); // Wait for transmit complete

    TI = 0;

}
void main() {

    serial_init();

    char msg[] = "HELLO";

    int i;

    for (i=0; msg[i]!='\0'; i++) {

        serial_tx(msg[i]);

    }

}

IV. 8096 Microcontroller

Functional Block Diagram & Superiority over 8051

Blocks:

1. CPU: 16-bit, register-ALU architecture (8-bit & 16-bit ops), 8-bit data bus.

2. Memory: 64KB ROM, 64KB RAM, separate I/O space (64KB). Memory mapping via MOVX/MOVC.

3. I/O Ports: 4 x 8-bit bidirectional ports (P0-P3), dual-function (address/data).

4. Timer/Counters: 2 x 16-bit timers, watchdog timer.

5. A/D Converter: 10-bit, 8-channel, successive approximation.

6. Serial Interface: Synchronous/async, baud rate from Timer 1.

7. Interrupt System: 8 sources, 4 priority levels, vector table at 2000H-20FFH.

8. Control/Status Register (CSR): Bit-addressable, controls interrupts, power-down, timer modes.

Superiority over 8051:

• 16-bit data path vs 8-bit.

• Higher performance (faster ALU, more registers).

• Integrated high-speed A/D (8 channels).

• More I/O ports with alternate functions.

• Advanced interrupt system (priority levels).

• Memory-mapped I/O vs 8051's special function registers.

Hardware Features

• I/O Ports: Bidirectional, can be programmed as input/output. P0/P2 also serve as address/data bus during external memory access.

• Memory Map:

  • Internal ROM: 0000H–0FFFH (4KB)

  • Internal RAM: 0000H–00FFH (256B) + 1000H–1FFFH (4KB)

  • External Memory: Up to 64KB each for code/data via MOVC/MOVX.

  • I/O Space: 00H–FFH (256 ports) via IN/OUT instructions.

Addressing Modes (with Examples)

Control and Status Register (CSR)

• Bit-addressable. Key bits:

  • IE (Interrupt Enable): Global interrupt enable.

  • IP (Interrupt Priority): Priority bits for each source.

  • T1CON/T0CON: Timer run/stop, mode bits.

  • PD (Power-Down): Set to enter low-power mode.

  • WS (Wait State): Insert wait states for slow external memory.

Register ALU

• Architecture: 8-bit data bus, 16-bit internal operations via register pairs (e.g., R2:R1 for 16-bit).

• Operations:

  • Arithmetic: ADD, ADDC, SUB, SUBB, MPY (16x16→32-bit), DIV (32/16→16).

  • Logic: AND, OR, XOR, NOT.

  • Shift: SHL, SHR (logical), RLC, RRC (through carry).

Memory Mapping

• Address Spaces: 64KB each for Code (MOVC), Data (MOVX), and I/O (IN/OUT).

• Internal/External Selection: MCS pin (Microcontroller Chip Select). Low = internal ROM enabled; high = external memory.

• Typical Map:

  
  0000H–0FFFH: Internal ROM (if MCS=0)
  
  0000H–00FFH: Internal RAM (always)
  
  1000H–1FFFH: External RAM/IO (if MCS=1)
  
  

Instruction Set Classification

V. Peripherals and Interfaces

Watchdog Timer (WDT)

• Purpose: System reliability; resets microcontroller if software hangs (fails to "kick" WDT).

• Operation: Independent timer; must be cleared (kicked) periodically by software before timeout. If timeout occurs, generates reset.

• Timing Diagram: Periodic "kick" pulses (write to WDT clear register) before timeout; if missing, reset pulse.

• Example: Set timeout 2 sec; software must write to WDT register every 1.5 sec.

Keyboard Interfacing

• Scanning: Matrix (rows x columns). Microcontroller scans rows sequentially, reads columns.

• Debouncing:

  • Hardware: RC filter, Schmitt trigger.

  • Software: Delay (10-20 ms) after key press, sample again.

• Processing: Scan code → ASCII conversion (lookup table).

• 8279 Modes:

  • Scanned Display Mode: Keyboard scanned, display refreshed automatically.

  • Interrupt Mode: Key press generates interrupt, FIFO stores code.

  • Strobed Input Mode: External strobe signal latches data.

Interrupt Systems

• Basics: Hardware signal (INT) interrupts normal flow; processor completes current instruction, saves context, jumps to ISR (Interrupt Service Routine).

• Vectored vs Non-Vectored: Vectored has fixed address per interrupt (jump via vector table); non-vectored jumps to common address, software identifies source.

• Polling: Software checks interrupt flags sequentially (slow, no priority).

• How Processor Checks:

  1. At end of each instruction, checks interrupt request lines.

  2. If enabled, acknowledges (INTA pin), gets vector (if vectored).

  3. Pushes PC/PSW, disables further interrupts (optional), jumps to ISR.

• Types:

  • External: Hardware pins (INT0, INT1).

  • Internal: Timer overflow, ADC complete, serial receive.

  • Software: TRAP, RST instructions (non-maskable).

  • Trap: Non-maskable, highest priority (e.g., power failure).

Interrupt Controllers

• Functional Block Diagram:

  
  Interrupt Sources → Priority Encoder → Control Logic → CPU (INT pin)
  
                     ↓
  
                 Vector Generator → Address Bus (to vector table)
  
  

• Operation:

  • Priority Resolution: Hardware encoder selects highest priority pending interrupt.

  • Nesting: Higher priority can interrupt lower priority ISR (if enabled).

  • EOI (End of Interrupt): Software writes to controller to signal ISR completion, allows next interrupt.

Serial Communication Standards: RS-232

• Signal Levels: ±3 to ±15 V (logic 1 = negative, 0 = positive). TTL (0-5V) incompatible; needs level shifter (MAX232).

• Pin Configuration (DB9):

  • Pin 2: RxD, Pin 3: TxD, Pin 4: RTS, Pin 5: CTS, Pin 6: DSR, Pin 7: GND, Pin 8: DCD, Pin 20: DTR.

• Handshaking Signals:

  • RTS (Request to Send): DTE (PC) asks DCE (modem) if ready to receive.

  • CTS (Clear to Send): DCE grants permission.

  • DTR (Data Terminal Ready): DTE ready.

  • DSR (Data Set Ready): DCE ready.

  • DCD (Data Carrier Detect): Modem connected to line.

  • Purpose: Flow control between devices, avoid data loss.

Real-Time Clock (RTC)

• Functionality: Keeps time (seconds, minutes, hours), date (day, month, year), often alarm and calendar. Battery-backed.

• Interfacing: Serial (I²C like DS1307, SPI) or parallel. Microcontroller reads/writes registers.

• Applications: Time-stamping events, scheduling tasks, data logging, alarm systems.

VI. Specific Microcontroller Families

16-bit PIC Microcontrollers (e.g., PIC24, dsPIC30)

• Architecture: Modified Harvard, 16-bit data, 24-bit instructions.

• Instruction Set: 16-bit, 16 registers (8 working, 8 shadow), single-cycle execution (most).

• Peripherals: ADC, DAC, multiple UARTs, SPI/I²C, PWM, comparators.

• Applications: Industrial control, motor control, consumer appliances.

32-bit dsPIC Microcontrollers

• dsPIC Features:

  • DSP Engine: 16-bit multiplier, 40-bit accumulator, barrel shifter, zero-overhead looping.

  • High-Speed: Up to 40 MIPS.

  • Motor Control Focus: Dedicated PWM, encoder interface, fault protection.

• Comparison with PIC32:

  • dsPIC: DSP-optimized, better for control loops, less RAM/Flash.

  • PIC32: General-purpose, MIPS core, more memory, better for user interfaces/network stacks.

• Applications: Digital motor control (ACIM, BLDC), power supplies, audio processing.

VII. Additional Topics from Short Notes

8279 Keyboard/Display Controller

• Internal Block Diagram:

  
  Keyboard Section: Scan Counter → Keyboard Debounce → FIFO (8x8)
  
  Display Section:  Display RAM (16x8) → Scan Counter → Display Drivers
  
  Control Logic:   Mode Setting, Interrupt Control
  
  CPU Interface:   Data Buffer, Address Decode, Control Pins (CS, A0, RD, WR)
  
  

• Operation Modes:

  • Input (Keyboard): Scanned (matrix scan), Interrupt (key press generates IRQ), Strobed (external strobe).

  • Output (Display): Scanned (multiplexed display), Right/Left entry.

• Programming: Write command to select mode, read keyboard FIFO, write display RAM.

Memory Mapping of 8096

• Address Space Allocation:

  • 0000H–0FFFH: Internal ROM (if MCS=0) or External ROM (if MCS=1).

  • 0000H–00FFH: Internal RAM (always accessible).

  • 1000H–1FFFH: External RAM/IO (via MOVX).

  • I/O Space: 00H–FFH (256 ports) accessed by IN/OUT (separate from memory space).

• Memory Selection Logic: MCS pin selects internal vs external ROM. RD/WR differentiate read/write cycles. ALE latches address during multiplexed bus cycles.

DSP Processors (Recap from II.E)

• Special Features:

  • Hardware MAC: Single-cycle multiply-accumulate.

  • Zero-Overhead Looping: Loop buffer avoids branch penalty.

  • Circular Buffering: Modulo addressing for FIR/IIR filters.

  • Harvard Memory: Separate program/data buses, often multi-banked.

  • Barrel Shifter: Bit-reverse, shift in one cycle.

• Role: Offload intensive math from GPP; used in audio, image, telecom, radar.

Real-Time Clock (RTC) (Recap from V.E)

• Core ICs: DS1307 (I²C), DS3231 (high accuracy), PCF8563.

• Interfacing Steps:

  1. Initialize I²C/SPI.

  2. Set time/date (BCD format).

  3. Read registers periodically.

  4. Handle alarm interrupts (if used).

• Applications: Data logging with timestamp, scheduled wake-up, time-based automation.

Exam Tips & Common Pitfalls

[!TIP] Timer Calculations (8051): Always compute timer tick = Crystal/12 (for standard mode). Reload value = 65536 - (Desired ticks). Verify with formula: $$\displaystyle f_{out} = \frac{\text{Crystal}}{12 \times (65536 - \text{TH0:TL0}) \times 2} $$ for square wave.

[!TIP] 8096 Instructions: MPY R1,R2 → 16x16=32-bit result in R3:R2:R1? No: MPY stores 32-bit in R3:R2 (R1 overwritten). DIV uses 32-bit dividend in R3:R2, divisor in R1, quotient in R2, remainder in R1. Overflow in DIV if dividend < divisor? Actually, if divisor=0 or quotient>16-bit → overflow flag set.

[!TIP] Serial Modes: Mode 2/3 use 9th bit for multiprocessor communication. In Mode 2, baud rate fixed (Fosc/32 or /64); Mode 3 variable from Timer 1. Mode 0 is synchronous shift register.

[!TIP] Watchdog Timer: Must be cleared periodically; if missed, resets system. Common pitfall: clearing WDT too early (wastes power) or too late (unexpected resets). Use interrupt to kick WDT if main loop hangs.

[!TIP] RS-232 Handshaking: RTS/CTS for hardware flow control; DTR/DSR for modem readiness. Without handshaking, risk of buffer overflow. MAX232 converts TTL to RS-232 levels.

[!TIP] Harvard vs Von Neumann: Harvard has separate code/data buses → no contention, faster, deterministic (critical for real-time). Von Neumann simpler, but bus contention can cause timing jitter. Most modern microcontrollers use modified Harvard (separate caches, unified main memory).