Microcontroller & Embedded system (EC-604 (A)) - Unit 4 Short Notes

UNIT 4: Microcontroller & Embedded System - Short Notes

I. Embedded System Fundamentals

Definition: An embedded system is a dedicated computer system designed to perform a specific function within a larger mechanical or electrical system, often with real-time computing constraints. It is embedded as part of a complete device.

Comparison: Embedded vs. General-Purpose Computing Systems

Key Characteristics:

• Dedicated Function: Built for a specific task.

• Resource Constraints: Limited CPU, memory, power.

• Real-Time Operation: Must respond within strict deadlines.

• Reliability & Robustness: Designed for long, fault-tolerant operation.

• Low Cost & Size: Optimized for the application.

• Low Power Consumption: Critical for portable/battery devices.

Quality Attributes:

• Reliability: Mean Time Between Failures (MTBF).

• Real-Time Performance: Meeting deadlines (hard vs. soft real-time).

• Power Efficiency: Battery life, heat dissipation.

• Robustness: Operates under harsh conditions (temp, noise).

• Security: Protection against unauthorized access.

• Maintainability: Ease of updates and repair.

Classification (Based on Performance & Complexity):

Design Metrics: Cost, Size, Power Consumption, Performance (MIPS), Time-to-Market, Reliability, Maintainability.

Major Application Areas:

• Consumer Electronics (TV, phone, camera)

• Automotive (engine, ABS, airbags)

• Industrial Automation (PLC, motor control)

• Telecommunications (routers, switches)

• Medical Devices (pacemaker, monitors)

• Aerospace & Defense (avionics, missiles)

• Networking (routers, modems)

[!TIP] Exam Focus: Be prepared to define embedded systems and contrast them sharply with PCs. Classification with examples is a frequent 7-mark question.

II. Microcontroller: 8051 Architecture and Programming

A. Timer/Counters

Modes of Operation (Timer 0 & 1):

Key Registers: TMOD (mode select), TCON (run/overflow flags), THx, TLx.

Programming Example: 1 kHz Square Wave on P2.3 (Timer 0, Mode 1, 11.0592 MHz)

#include <reg51.h>

void main() {

    TMOD = 0x01;      // Timer 0, Mode 1 (16-bit)

    TH0 = 0xFC;       // Preload for 1ms delay (11.0592MHz)

    TL0 = 0x66;       // (65536 - 11059.2/12/1000) = 0xFC66

    ET0 = 0;          // Disable interrupt

    TR0 = 1;          // Start Timer 0

    while(1) {

        if(TF0 == 1) { // Check overflow

            TF0 = 0;   // Clear flag

            TH0 = 0xFC; // Reload

            TL0 = 0x66;

            P2_3 = ~P2_3; // Toggle pin

        }

    }

}

Applications: Precise time delays, baud rate generation (Mode 2), event counting, pulse width measurement.

B. Serial Communication

Serial Modes (SCON Register):

Mode 1 vs. Mode 3 Comparison:

Embedded C Program: Transmit "HELLO" in Mode 1 (9600 baud, 11.0592 MHz)

#include <reg51.h>

void serial_init() {

    SCON = 0x50;      // Mode 1, 8-bit UART, enable receive

    TMOD = 0x20;      // Timer 1, Mode 2 (auto-reload)

    TH1 = 0xFD;       // 9600 baud @ 11.0592MHz (256 - 11059200/(12*32*9600))

    TR1 = 1;          // Start Timer 1

    TI = 1;           // Ready to transmit

}
void serial_tx(char data) {

    SBUF = data;      // Load data

    while(!TI);       // Wait for transmission complete

    TI = 0;           // Clear flag

}
void main() {

    serial_init();

    char msg[] = "HELLO";

    int i;

    for(i=0; msg[i]!='\0'; i++) {

        serial_tx(msg[i]);

    }

}

RS-232 Standard:

• Role: Defines electrical characteristics & signal timing for serial data exchange between DTE (PC) & DCE (modem).

• Key Signals:

  • TXD (Transmit Data): DTE -> DCE

  • RXD (Receive Data): DTE <- DCE

  • RTS (Request to Send): DTE asks permission to send.

  • CTS (Clear to Send): DCE grants permission.

  • DTR (Data Terminal Ready), DSR (Data Set Ready): Link status.

• Voltage Levels: Logic '1' = -3V to -15V, Logic '0' = +3V to +15V (MAX232 used for level conversion).

• Handshaking: Hardware (RTS/CTS) or software (XON/XOFF) to control data flow.

C. Interfacing and System Design

1. ADC Interfacing (e.g., ADC0804)

• Circuit: Analog Input -> ADC0804 -> Data Bus (P1); Control: CS, RD, WR, INTR to 8051 I/O pins.

• Start of Conversion (SOC): Pulse WR low (start) after setting CS low.

• End of Conversion (EOC): INTR goes low when conversion complete.

• Read Data: Pulse RD low after INTR low; data appears on bus.

• Methods: Polling (check INTR), Interrupt (connect INTR to INT0/1).

2. DAC Interfacing (e.g., DAC0800)

• Circuit: Data Bus (P1) -> DAC0800; Control: CS, WR; Output: I_out -> Op-amp (I-to-V) -> Analog Output.

• Timing: Load data on bus, pulse WR low. Conversion is immediate (current output).

• Application: Waveform generation (sine, square), analog control (motor speed).

3. Stepper Motor Interfacing

• Circuit: 8051 Port Pins -> ULN2003 (Darlington array driver) -> Stepper Motor coils.

• Unipolar (5/6-wire): Sequence: A->AB->B->BC->C->CD->D->DA.

• Bipolar (4-wire): Sequence: AB->BC->CD->DA.

• Programming: Generate timing delays between steps using Timer.

4. 8051-Based Data Acquisition System

• Hardware Components:

  1. Sensor/Transducer: Converts physical parameter (temp, pressure) to electrical signal.

  2. Signal Conditioning: Amplification, filtering (op-amps) to match ADC input range.

  3. ADC: Converts analog signal to digital (e.g., ADC0804, 0809).

  4. 8051 Microcontroller: Controls ADC, processes data, stores/communicates.

  5. Display/Communication: LCD/7-seg for local display, UART/RS-232 for PC, memory (EEPROM) for logging.

  6. Power Supply: Regulated 5V for 8051 & peripherals.

• Operation: Sensor -> Conditioning -> ADC -> 8051 (reads, processes) -> Output.

III. Microcontroller: 8096 Architecture and Programming

A. Functional Block Diagram & Overview

Explanation of Blocks:

• CPU: 16-bit, register-register architecture. Registers: Accumulator (A), B (for multiply), R0-R15 (general purpose, R14=SP, R15=PC).

• Memory: 4K ROM (internal), 232 Byte RAM (internal). External memory expandable to 64KB.

• I/O Ports: Four 8-bit ports (P0-P3), multiplexed with address/data bus. P4 is dedicated I/O.

• Timer: 16-bit, can be used for timing, counting, or baud rate.

• A/D Converter: 8-channel, 8-bit, successive approximation.

• Serial Interface: Full-duplex UART, programmable baud rate.

• Interrupt System: 5 interrupt sources (external, timer, serial, software), 2 priority levels.

Superiority over 8051:

1. 16-bit Architecture: Higher performance, larger data/address space.

2. Built-in Peripherals: ADC, PWM, more I/O, enhanced serial.

3. Register Set: More general-purpose registers (R0-R15) reduce memory access.

4. Instruction Set: Efficient 16-bit operations (e.g., ADD, MPY).

B. Registers and I/O System

• I/O Ports (P0-P4):

  • P0-P3: Multiplexed with address/data bus (need ALE to latch address).

  • P4: Dedicated I/O port.

  • Programming: Write to port latch (e.g., LD P1, #0FFH). Read from port buffer.

• Control & Status Registers:

  • INT_MASK: Enable/disable interrupts.

  • INT_PEND: Pending interrupt flags (write 1 to clear).

  • TIMER_CTL: Timer control (run, mode, prescaler).

  • AD_CTL: ADC control (start channel, conversion start).

  • BAUD_RATE: Sets serial baud rate.

• Memory Organization:

  • Internal: 4K ROM @ 0x0000-0x0FFF, 232 RAM @ 0x0000-0x00E8 (overlaps with I/O/registers).

  • External: Up to 64KB each for program/data. PSEN for program fetch, RD/WR for data.

  • I/O Mapped: Ports & control registers accessed with ANL/ORL/XRL instructions (special I/O space).

C. ALU and Instruction Set

Register ALU: Performs 16-bit operations on registers. Flags: Carry (C), Overflow (V), Zero (Z), Sign (S), Parity (P).

Addressing Modes:

Instruction Set Classification:

• Data Transfer: LD, ST, PUSH, POP, LDB, STB (byte).

• Arithmetic: ADD, SUBB, INC, DEC, MPY (multiply, result in A:B), DIV (divide A by B).

• Logical: AND, OR, XOR, NOT, CLR, SETC.

• Branch: JMP, JBC, JC, JNC, JZ, JNZ.

• Subroutine: CALL, RET.

• I/O & Control: ANL/ORL/XRL (to I/O space), DI, EI, NOP.

Code Analysis Example:

LD R1, #05H    ; R1 = 0x0005

LD R2, #03H    ; R2 = 0x0003

MPY R1, R2     ; A:B = R1 * R2 = 0x0005 * 0x0003 = 0x000F (A=0x00, B=0x0F)

ST R1, 0200H   ; Store R1 (0x0005) at 0200H? **NO!** MPY result in A:B.

• i) Value at 0200H: 0x0005 (original R1 value). MPY result is in A:B (A=0x00, B=0x0F), not stored in R1.

• ii) If MPY -> DIV: DIV R1, R2 divides A:B by R2. A:B must be set up. If A:B=0x000F, R2=0x0003, result: A=quotient=0x0005, B=remainder=0x0000.

• iii) Overflow Risk: Yes for DIV. If divisor (R2) is zero, result undefined. For MPY, max 16-bit * 16-bit = 32-bit (fits in A:B), no overflow flag for MPY. DIV can cause divide-by-zero error.

D. System Integration Aspects

• Role: Used in motor control (PWM output), data acquisition (built-in ADC), industrial controllers, instrumentation.

• Advantages: Integrated ADC reduces external components; 16-bit processing for precision; multiple timers/PWM.

IV. Processor Architectures for Embedded Systems

A. Architectural Paradigms

CISC vs RISC:

B. Specialized Processors

1. ARM Processor:

• Architecture: Load/Store, RISC, fixed 32-bit (ARM) or 16/32-bit (Thumb) instructions.

• Key Features: Multiple operating modes (User, FIQ, IRQ, SVC), banked registers for fast context switch, extensive conditional execution, pipelining (typically 3-5 stages).

• Significance in Mobile: Power efficiency (low power per operation), performance-per-watt, licensable core (custom SoC), rich ecosystem. Dominates smartphones/tablets.

2. DSP (Digital Signal Processor):

• Special Features:

  • Hardware Multiplier-Accumulator (MAC): Single-cycle multiply-accumulate.

  • Zero-Overhead Looping: Hardware loop counters/buffers.

  • Pipelining: Deep pipelines for high throughput.

  • Special Addressing: Bit-reversed, circular buffers for FFT.

  • Fixed/Floating-Point Units: Optimized for math-intensive ops.

• Role & Advantage: Superior for signal processing (audio, video, comms) vs GPPs. Executes algorithms (FIR/IIR filters, FFT, convolution) much faster with lower clock speed/power.

C. Processor Classification and Selection

Selection Criteria: Performance (MIPS, DMIPS), Cost (unit, NRE), Power (mW/MHz), Flexibility (reprogrammability), Time-to-market, Ecosystem (tools, libraries).

[!TIP] Exam Focus: Von Neumann vs Harvard and CISC vs RISC are almost always in exams. Know the Harvard advantage (parallel fetch) and RISC load/store rule. ARM's power efficiency for mobile is key.

V. Interrupt Systems

Concept: Mechanism allowing peripheral/event to interrupt normal program flow, forcing CPU to execute a dedicated service routine (ISR). Enables real-time response and efficient CPU use (vs. polling).

Types:

• Hardware Interrupts:

  • External: From pins (e.g., INT0, INT1 on 8051).

  • Internal/On-chip: From peripherals (Timer overflow, ADC complete, UART receive).

• Software Interrupts:

  • Trap/Exception: Generated by CPU on error (divide-by-zero, invalid opcode).

  • Software Interrupt Instruction: e.g., INT in x86, SWI in ARM (calls OS service).

Handling Mechanism:

1. Interrupt Occurs: Peripheral sets interrupt flag/request line.

2. CPU Checks: After each instruction (or at interruptible points), CPU checks pending interrupts (if interrupts enabled).

3. Response Sequence:

   • Finish current instruction.

   • Save Context: Push PC (and sometimes PSW/registers) onto stack.

   • Fetch ISR Address: From Interrupt Vector Table (fixed memory locations, e.g., 0003H for INT0 in 8051).

   • Branch to ISR.

4. ISR Execution: Service routine runs (must save/restore used registers).

5. Return: RETI (8051) or POP PC restores context, resumes main program.

Interrupt Priority & Nesting:

• Priority: Hardware or software defined. Higher priority interrupt can preempt lower priority ISR.

• Nesting: When a higher-priority interrupt arrives during a lower-priority ISR, CPU saves current context, serves higher, then returns.

• Enabling/Disabling: Global (EA in 8051, CPSID in ARM) and individual interrupt enable bits.

Interrupt Controller (e.g., 8259A):

• Function: Manages multiple interrupt sources (up to 8 or cascaded to 64), prioritizes, and presents a single interrupt line to CPU.

• Block Diagram: Interrupt Request Lines (IR0-IR7) -> Priority Resolver -> Interrupt Request Register (IRR) -> In-Service Register (ISR) -> Interrupt Controller Logic -> INT to CPU.

• Operation: When interrupt occurs, IRR bit set. Priority resolver determines highest priority pending interrupt. Sends INT to CPU. CPU acknowledges (INTA), controller puts vector on data bus. Cascading allows multiple 8259s.

VI. Peripherals and System Components

A. Watchdog Timer (WDT)

• Operation: Independent timer that must be periodically reset (kicked) by software. If software hangs/hangs, WDT times out and generates a system reset.

• Timing Diagram:

  
  Software Kicks (clear WDT) -> WDT Counter Reset -> Never Timeout -> Normal Operation
  
  Software Hangs -> No Kicks -> Counter Reaches 0 -> Reset Signal -> System Restart
  
  

• Role in Reliability: Recovers from software faults (infinite loops, lock-ups), improves robustness in harsh/unattended environments.

• Implementation:

  • Hardware WDT: Dedicated chip (e.g., MAX813) or built-in MCU peripheral (e.g., PIC, ARM).

  • Software WDT: Timer interrupt that must be cleared; less reliable if interrupt system fails.

B. Keyboard Controller (8279)

• Key-Press Scanning (Matrix): Keyboard arranged in rows & columns. Controller:

  1. Drives one row low (others high).

  2. Reads column lines to see if any key in that row is pressed (low).

  3. Cycles through all rows.

• Debouncing:

  • Hardware: RC filter (low-pass) on key signal.

  • Software: Delay (10-20ms) after first detection, re-check to confirm stable state.

• Modes of 8279:

  • Encoded Scan: Internal 2-bit counter decodes row scan (4x4 matrix).

  • Decoded Scan: External decoder (e.g., 74LS138) for larger matrices.

  • FIFO: 8-byte First-In-First-Out buffer stores key codes; interrupt on non-empty.

• Processing: Key press generates make code, release generates break code (if 2-key rollover). Controller sends code to CPU via data bus. Interrupt-driven preferred over polling.

C. Communication and Timing Peripherals

RS-232 (Recap): See II.B. Key for serial port connection to PC/legacy devices.

Real-Time Clock (RTC):

• Functionality: Maintains time (HH:MM:SS) and date (YY-MM-DD) independently, often with battery backup. Provides alarm/interrupt at specific time.

• Interfacing: Typically via I2C (DS1307, PCF8563) or SPI. Simple serial protocol to read/write time registers.

• Use: Time-stamping data logs, scheduled tasks, wake-up from sleep.

VII. Specialized Microcontrollers

1. 16-bit PIC Microcontrollers (e.g., PIC24, dsPIC30)

• Key Features:

  • 16-bit data path, 24-bit instruction word.

  • Modified Harvard architecture (separate instruction/data buses, but with data memory access to program space).

  • RISC-like: Single-cycle instructions (except branches, multiplies).

  • Rich Peripherals: Multiple timers, ADC, PWM, UART, SPI, I2C, CAN.

  • Interrupt Controller: Priority-based nested interrupts.

• Typical Applications: Industrial control (PLC I/O), automotive (body electronics), motor control, instrumentation.

2. 32-bit dsPIC Microcontrollers (Digital Signal Controller)

• Key Features:

  • 32-bit data path, 24-bit instruction word (like PIC24).

  • DSP Engine: Hardware MAC unit (Multiply-Accumulate), barrel shifter, zero-overhead looping.

  • High Speed: Up to 40+ MIPS, with DSP instructions executing in 1 cycle.

  • Peripherals: Same as PIC24 + high-speed PWM, dedicated motor control PWM modules.

• Typical Applications: Digital Signal Processing (audio filtering, speech recognition), advanced motor control (FOC - Field Oriented Control), power conversion (SMPS), industrial drives.

[!TIP] Exam Focus: For specialized MCUs, know the key feature (DSP engine for dsPIC) and primary application domain (motor control, DSP). Contrast with general 16-bit PIC.