Microcontroller & Embedded system (EC-604 (A)) - Unit 3 Short Notes

UNIT 3: Microcontroller & Embedded System

I. Embedded System Fundamentals

Definition and Core Concept

An embedded system is a dedicated computer system designed to perform specific control functions within a larger mechanical or electrical system. It is typically embedded as an integral part of the device.

Key Distinction from General-Purpose Computing:

• Embedded System: Single-purpose, resource-constrained, real-time, often reactive to environment. Example: Microwave oven controller.

• General-Purpose System: Multi-purpose, high resources (CPU, memory, I/O), user-programmable for diverse tasks. Example: Desktop PC.

Characteristics of Embedded Systems

• Single-functioned: Executes a specific program repeatedly.

• Tightly constrained: Limited by cost, size, power, performance.

• Reactive & Real-time: Must respond to external events within strict deadlines (hard/soft real-time).

• Often operates in harsh environments.

• Low power consumption is critical for battery-operated devices.

• No standard user interface (often no keyboard/monitor).

Quality Attributes (Non-Functional Requirements)

Design Metrics (Quantifiable Goals)

Primary trade-offs exist between:

1. Performance (MIPS, MHz)

2. Power (mW)

3. Cost (USD)

4. Size (mm²)

5. Memory (KB)

Classification Based on Performance & Complexity

Major Application Areas

• Automotive: Engine control, ABS, airbags, infotainment.

• Consumer Electronics: TVs, cameras, washing machines, wearables.

• Industrial: PLCs, robotics, process control, instrumentation.

• Telecom: Switches, routers, modems, mobile phones.

• Aerospace & Defense: Flight control, radar, missile guidance.

• Medical: Pacemakers, imaging systems, patient monitors.

II. 8051 Microcontroller

A. Timer/Counter Operations

Core Concept: Two independent 16-bit timers/counters (Timer 0, Timer 1). Can be configured in 4 modes.

• Mode 0 (13-bit): Legacy mode, THx holds upper 8 bits, TLx holds lower 5 bits.

• Mode 1 (16-bit): Full 16-bit timer/counter (THx:TLx as 16-bit register). Most common.

• Mode 2 (8-bit auto-reload): TLx holds count, THx holds reload value. Used for baud rate generation.

• Mode 3 (Split Timer): Timer 0 splits into two 8-bit timers; Timer 1 stops (can be used as baud rate generator).

Programming Timer 0 in Mode 1 for Square Wave Generation (11.0592 MHz Crystal):

Goal: Generate 1 kHz square wave on P2.3.

Formula: Frequency = Crystal Freq / (12 * (65536 - TH0_TL0))

1. Calculate reload value: TH0_TL0 = 65536 - (11059200 / (12 * 1000)) = 65536 - 921.6 ≈ 64574 = 0xFC66.

2. Initialize TMOD: TMOD = 0x01 (Timer0 Mode1).

3. Load TH0, TL0: TH0 = 0xFC; TL0 = 0x66;.

4. Start timer: TCON = 0x10 (TR0=1).

5. Toggle P2.3 in ISR (TF0 interrupt) or poll TF0 flag.

B. Serial Communication

Modes of Operation (SCON register bits SM0, SM1):

Detailed Comparison: Mode 1 vs Mode 3

Programming Serial Transmission in Embedded C (Mode 1, 11.0592 MHz, 9600 baud):

#include <reg51.h>

void serial_init() {

    SCON = 0x50; // 8-bit UART, enable receiver

    TMOD &= 0x0F; // Clear Timer1 bits

    TMOD |= 0x20; // Timer1 Mode2 (8-bit auto-reload)

    TH1 = 0xFD;   // Reload value for 9600 baud @ 11.0592MHz

    TL1 = 0xFD;

    TR1 = 1;      // Start Timer1

    TI = 0;       // Clear transmit flag

}
void serial_tx_char(char c) {

    SBUF = c;

    while(!TI); // Wait for transmission complete

    TI = 0;

}
void main() {

    serial_init();

    serial_tx_char('H');

    serial_tx_char('E');

    serial_tx_char('L');

    serial_tx_char('L');

    serial_tx_char('O');

    while(1);

}

C. Interfacing and Applications

1. DAC Interfacing (e.g., DAC0800)

• Circuit: 8051 P0 (8-bit data) → DAC0800 inputs. DAC reference voltage (Vref) sets output range. Output current Iout = (D/256) * (Vref/ R). Requires current-to-voltage op-amp converter at output.

• Timing Diagram: Data valid → CS & WR low pulse (min 500ns) → analog output settles.

• Application: Waveform generation (sine, square), analog control signals, audio output.

2. Stepper Motor Interfacing

• Circuit: 8051 port pins → Driver IC (e.g., ULN2003/ULN2803) → Stepper motor coils (4-phase or 2-phase).

• Sequence: Full-step (4-phase sequence) or Half-step (8-phase sequence) pulses generated by software delay loops.

• Control: Speed by delay between steps, direction by sequence order.

• Application: Printers, plotters, CNC machines, robotics.

3. Design of 8051-based Data Acquisition System (DAS)

Block Diagram & Components:

1. Sensor/Transducer: Converts physical parameter (temp, pressure) to analog signal.

2. Signal Conditioning: Amplifier, filter (anti-aliasing) to bring signal to ADC range.

3. Analog-to-Digital Converter (ADC): e.g., ADC0804 (8-bit). Controlled by 8051 WR, RD, CS pins.

4. 8051 Microcontroller: Controls ADC start, reads data, processes, stores.

5. Memory: External EEPROM/Flash for data logging.

6. Display/Output: LCD (via P0/P2) or serial to PC.

7. Power Supply: Regulated 5V for MCU & logic, isolated supply for analog front-end.

Operation: MCU triggers ADC → waits for conversion → reads digital data → processes (calibration, scaling) → stores/displays.

III. 8096 Microcontroller

A. Architecture and Overview

Functional Block Diagram Explanation:

1. CPU (16-bit): Central processing unit with 16-bit data bus & ALU.

2. Register ALU (RAL): High-speed arithmetic unit for multiply/divide.

3. Memory Interface: Generates control signals for external memory.

4. I/O Ports: 4 x 8-bit parallel ports (P0-P3), multiplexed with address/data bus.

5. Timer/Counter: 16-bit timer with 4 modes, event counter.

6. Serial Port: Full-duplex UART.

7. A/D Converter: 10-bit, 8-channel multiplexed ADC.

8. Watchdog Timer: For system recovery.

9. High-Speed I/O Section: Special pins for PWM, pulse measurement.

10. Interrupt Controller: 5 interrupt sources with priority.

Superiority over 8051:

• 16-bit data path & ALU vs 8-bit → faster arithmetic.

• On-chip 10-bit ADC (8051 requires external ADC).

• Register ALU (RAL) for fast 16x16 multiply/divide in 3.5-7 µs.

• More I/O pins (40-pin vs 8051's 40-pin but more multiplexing options).

• Enhanced timer with capture/compare.

• Higher clock speed (up to 12 MHz vs 8051's 12-24 MHz typical).

• More memory address space (64KB data, 64KB program).

B. Registers and I/O

Control and Status Register (CSR)

• Function: Controls I/O port modes (input/output), serial port mode, and indicates status of interrupts, A/D conversion.

• Key Bits:

  • PORT-MODE bits (PM0-PM3): Configure P0-P3 as I/O or address/data bus.

  • SERIAL-MODE bits (SM0, SM1): UART mode select.

  • A/D CONVERSION COMPLETE flag.

  • TIMER OVERFLOW flag.

  • INTERRUPT PENDING bits.

I/O Ports Structure

• P0-P3: 8-bit ports. Function determined by CSR PM bits.

  • PMx = 0: Port acts as I/O (quasi-bidirectional like 8051).

  • PMx = 1: Port used for address/data bus multiplexing (external memory access).

• Operation: Writing 1 to port bit makes it input (high-impedance). Writing 0 drives low.

Register ALU (RAL)

• Significance: Dedicated hardware for 16x16 multiplication and 32/16 division.

• Operation: Uses registers R0 (multiplicand), R1 (multiplier), R2 (product high), R3 (product low). MPY & DIV instructions execute in fixed cycles (~3.5-7 µs at 12 MHz), much faster than software loops on 8051.

• Overflow: DIV instruction causes software trap if divisor is zero or result > 16 bits.

C. Memory Organization

• Separate Program & Data Spaces: Harvard-like but can be unified.

• Address Spaces:

  • 64KB Program Memory (PMEM): Addresses 0000H-FFFFH. Can be internal ROM/EPROM or external.

  • 64KB Data Memory (DMEM): Addresses 0000H-FFFFH. Internal RAM (256 bytes) + external.

• Internal RAM (256 bytes):

  • 00H-7FH: General-purpose registers, bit-addressable area.

  • 80H-FFH: Special Function Registers (SFRs) including ports, timer, CSR, etc.

• External Memory: Accessed via multiplexed P0/P1 bus when PMx=1.

D. Addressing Modes (with Code Examples)

Analysis of Past Paper Code:

LD R1, #05H   ; R1 = 0x0005 (Immediate)

LD R2, #03H   ; R2 = 0x0003 (Immediate)

MPY R1, R2    ; R1 = R1 * R2 = 0x0005 * 0x0003 = 0x000F (R2:R1 = 32-bit product)

ST R1, 0200H  ; Store R1 (0x000F) at memory 0200H

i) Value at 0200H: 0x000F (15 decimal).

ii) If MPY replaced by DIV: DIV R1, R2 → R1 = R1 / R2 = 5 / 3 = 1 (quotient), R2 = remainder = 2. Store would be 0x0001.

iii) Overflow Risk in DIV: Yes. If divisor (R2) is zero → software trap (non-maskable interrupt). If dividend > 0xFFFF (16-bit) → quotient > 16 bits → overflow flag set and result undefined.

E. Instruction Set Classification

IV. Processor Architectures for Embedded Systems

A. Architecture Types

Von Neumann vs Harvard

RISC vs CISC

B. Specific Processors

ARM Processor Architecture

• RISC Features: Load/Store architecture, fixed 32-bit (ARM state) or 16-bit (Thumb state) instructions, large register file (R0-R15), conditional execution.

• Pipeline: Classic 3-stage (fetch, decode, execute) or advanced (e.g., ARM7: 3-stage, ARM9: 5-stage).

• Use in Mobile: Dominant due to power efficiency, high performance/Watt, licensable core (SoC integration), extensive ecosystem. Found in >95% of smartphones.

DSP Processors (Digital Signal Processors)

• Role: Optimized for high-speed numeric processing, especially multiply-accumulate (MAC) operations on streaming data (audio, video, telecom).

• Special Features vs GPP:

  1. Harvard Architecture: Separate program/data buses → simultaneous instruction/data fetch.

  2. Deep Pipelines: 6-10 stages for high clock rates.

  3. Hardware MAC Unit: Single-cycle multiply-accumulate.

  4. Zero-Overhead Looping: Hardware support for repetitive DSP algorithms.

  5. Special Addressing Modes: Bit-reversed, circular buffering for FFT.

  6. Fixed-Point Arithmetic: Native support, fast.

• Example: TI TMS320C5000 (C55x), ADI SHARC, Freescale (NXP) DSP56k.

C. Processor Classifications & Selection Criteria

16-bit PIC & 32-bit dsPIC (Microchip):

• 16-bit PIC (e.g., PIC24): 16-bit data path, RISC, rich peripherals (ADC, PWM, CAN), low power. Apps: Industrial control, consumer, automotive body.

• 32-bit dsPIC: Combines 16-bit DSP engine (MAC, barrel shifter) with PIC24 MCU core. Apps: Motor control (FOC), digital power, audio processing.

V. Peripheral Interfaces and Controllers

A. Watchdog Timer (WDT)

• Operation: Independent timer that must be periodically "kicked" (reset) by software. If software hangs (fails to kick), WDT times out and generates a reset or interrupt to recover system.

• Timing Diagram:

  
  Software Kick ----> WDT Reset ----> (Timeout Period) ----> Reset/Interrupt
  
  

• Role in Reliability: Fault detection & automatic recovery from software lock-ups, electromagnetic interference (EMI) glitches. Critical in safety-critical systems (automotive, medical).

• Implementation: Can use a regular timer/counter with a long timeout, configured to trigger system reset on overflow. Software writes a specific sequence to a control register to clear it.

B. Keyboard Controller (8279)

Internal Block Diagram & Explanation:

• Keyboard Section: Scans matrix (e.g., 8x8) for key closures. Debounces in hardware/software. Encodes key position to scan code.

• Display Section: Drives multiplexed LED/LCD displays (up to 16 digits/segments). Stores display RAM.

• FIFO (8-byte): Stores key codes (with shift/control status). CPU reads via data bus.

• Control Unit: Registers for mode setting (encoded/decoded, scan rate), interrupt generation on FIFO not empty/not full.

Key-Press Scanning (Matrix Scanning):

1. Drive one row line low (others high).

2. Read column lines. Low on any column → key pressed at (row, column).

3. Repeat for all rows.

4. Debouncing: Hardware (RC filter) or software (sample key state multiple times over 10-20ms).

Processing Key Codes & Modes:

• Encoded Mode: 8279 returns scan code (row+col). CPU needs lookup table for ASCII.

• Decoded Mode: 8279 returns ASCII code directly (requires 8279 to be programmed with key map). Simpler for CPU.

C. Interrupt Controllers

Functional Block Diagram & Explanation:

• Purpose: Manage multiple interrupt sources, prioritize, and present single interrupt line to CPU.

• Blocks:

  1. Interrupt Request (IRQ) Lines: Inputs from peripherals.

  2. Priority Encoder: Determines highest priority pending interrupt.

  3. Interrupt Service Register (ISR): Bits set when IRQ active, cleared by CPU on ISR entry.

  4. Interrupt Mask Register (IMR): Masks (disables) specific interrupts.

  5. Cascade Buffer: For cascading multiple controllers (e.g., 8259A).

  6. Interrupt Output: Single INT line to CPU.

Types of Interrupts & Microprocessor Interface:

How CPU Checks: After each instruction cycle, CPU checks interrupt flags (in status register) and interrupt controller's output. If enabled and pending, it initiates interrupt acknowledge cycle.

D. Serial Communication Standards: RS-232

• Role: Standard for serial binary data exchange between DTE (Data Terminal Equipment, e.g., PC) and DCE (Data Circuit-terminating Equipment, e.g., modem).

• Voltage Levels: Mark (logic 1): -3V to -15V. Space (logic 0): +3V to +15V. (Inverted, opposite of TTL/CMOS).

• Main Signals:

  • TXD (Transmit Data): DTE → DCE.

  • RXD (Receive Data): DTE ← DCE.

  • RTS (Request To Send): DTE → DCE, requests permission to send.

  • CTS (Clear To Send): DCE → DTE, grants permission.

  • DTR (Data Terminal Ready): DTE → DCE, DTE is powered on.

  • DSR (Data Set Ready): DCE → DTE, DCE is powered on.

  • GND: Signal ground.

Handshaking Signals Purpose:

• Hardware Flow Control: Uses RTS/CTS to prevent data overflow. DTE asserts RTS when its buffer has space; DCE asserts CTS when it can receive.

• Modem Control: DTR/DSR indicate modem readiness. DCD (Data Carrier Detect) indicates carrier signal from remote modem.

E. Other Peripherals

Real-Time Clock (RTC)

• Functionality: Keeps track of current time (seconds, minutes, hours, date, month, year) independently of main CPU. Often battery-backed (CMOS RAM + crystal).

• Interfacing: Typically via I²C (e.g., DS1307) or SPI serial bus. MCU reads/writes time/date registers and configures alarm/interrupt.

• Application: Data logging with timestamp, scheduled events, time-sensitive control.

Exam Tips & Common Pitfalls:

• 8051 Timer Mode 1: Always remember reload value = 65536 - (Crystal/(12 * Desired_Freq)). For 1kHz @ 11.0592MHz, it's 64574 (0xFC66).

• 8096 MPY/DIV: MPY stores 32-bit product in R2:R1. DIV quotient in R1, remainder in R2. DIV by zero causes trap.

• RS-232 Voltage: Negative = logic 1, Positive = logic 0. NOT TTL compatible – requires MAX232 level shifter.

• Watchdog: Must be "kicked" periodically in main loop. If ISR takes too long, WDT may expire – place kick in main loop, not ISR.

• Harvard vs Von Neumann: Key is separate vs unified memory/buses. Most modern MCUs are Modified Harvard (separate buses but can access program memory as data).

• RISC vs CISC: RISC = simple, load/store, many regs, pipelined. CISC = complex, memory access in many instructions, variable length.

• 8279 Modes: Encoded = scan code (CPU decodes). Decoded = ASCII (8279 decodes).