Microcontroller & Embedded system (EC-604 (A)) - Unit 2 Short Notes

UNIT 2: Microcontroller & Embedded Systems

1.0 Embedded System Fundamentals

1.1 Definition and Core Concept

An embedded system is a dedicated computer system designed to perform a specific function within a larger mechanical or electrical system. It is typically embedded as an integral part of the device.

Core Concept: It is a combination of hardware (microcontroller/microprocessor, memory, I/O interfaces) and software (firmware) tailored for a particular application, often with real-time constraints.

1.2 Comparison: Embedded System vs. General-Purpose Computing System

1.3 Key Characteristics

• Dedicated Function: Built for a specific application.

• Resource Constraints: Limited processing power, memory, and power.

• Real-Time Operation: Must respond to external events within strict time limits (hard/soft real-time).

• Low Cost, Size, Power: Highly optimized for these metrics.

• High Reliability & Robustness: Often operates in harsh environments for long periods without maintenance.

• Software in Hardware: Tight coupling between software (firmware) and hardware.

1.4 Quality Attributes (Non-Functional Requirements)

• Performance: Execution speed, throughput, latency.

• Power Consumption: Critical for battery-operated devices.

• Cost: Total cost of ownership (hardware + development).

• Size/Footprint: Physical dimensions.

• Reliability: Mean Time Between Failures (MTBF).

• Maintainability: Ease of repair/upgrade.

• Scalability: Ability to handle increased load or add features.

1.5 Design Metrics and Trade-offs

Design is a constant balancing act:

• Performance vs. Power: Higher performance usually means higher power.

• Cost vs. Features/Performance: More features increase cost.

• Size vs. Capability: Smaller size may limit I/O or processing.

• Time-to-Market vs. Optimization: Rushed design may sacrifice efficiency.

Key Trade-off: Performance-Power-Cost triangle. Optimizing two often degrades the third.

1.6 Classification Based on Performance & Complexity

1.7 Common Application Areas

• Consumer Electronics: TVs, cameras, gaming consoles.

• Automotive: Engine control, ABS, airbags, infotainment.

• Industrial: PLCs, robotics, process control, instrumentation.

• Telecommunications: Routers, switches, modems.

• Aerospace & Defense: Flight control, radar, navigation.

• Medical: Pacemakers, monitors, imaging equipment.

• Networking: Firewalls, servers (embedded variants).

2.0 8051 Microcontroller

2.1 Architecture and Functional Overview

Architecture: Harvard Architecture (separate program and data memory buses), 8-bit CPU. Key Blocks:

1. CPU: 8-bit ALU, accumulator (A), B register, program counter (PC), stack pointer (SP), PSW (Program Status Word).

2. Memory: 4KB on-chip ROM (code), 128B on-chip RAM (data), external memory expandable to 64KB each.

3. I/O Ports: Four 8-bit parallel ports (P0-P3), multiplexed with other functions.

4. Timers/Counters: Two 16-bit timers (Timer 0, Timer 1), Timer 2 in 8052.

5. Serial Port: Full-duplex UART (Universal Asynchronous Receiver/Transmitter).

6. Interrupts: 5 sources (2 external, 2 timers, 1 serial).

2.2 Timer/Counter Operations

Modes of Operation (for Timer 0 & 1):

Programming Timer 0 in Mode 1 for 1 kHz Square Wave @ P2.3 (11.0592 MHz crystal):

• Machine Cycle: $$\displaystyle T_{cy} = 12 / f_{osc} = 12 / 11.0592 \times 10^6 \approx 1.085\ \mu s $$

• Desired Period: $$\displaystyle T = 1/1000 = 1\ ms $$

• Timer Count for 50% Duty (toggle on overflow): $$\displaystyle N = (T/2) / T_{cy} = 0.5ms / 1.085\mu s \approx 461 $$

• Initial Count (16-bit): $$\displaystyle 65536 - 461 = 65075 = 0xFE3B $$

• TH0 = 0xFE, TL0 = 0x3B

// Embedded C Code Snippet

TMOD = 0x01; // Timer0, Mode1

TH0 = 0xFE; // Load initial count for 1kHz

TL0 = 0x3B;

TCON = 0x10; // Start Timer0 (TR0=1)

while(1) {

if(TF0) { // Check overflow flag

    TF0 = 0;

    P2 ^= 0x08; // Toggle P2.3

    TH0 = 0xFE; // Reload

    TL0 = 0x3B;

}

}

2.3 Serial Communication (UART)

All Four Modes:

Comparative Analysis: Mode 1 vs. Mode 3

Programming Serial Transmission in Mode 1 (Transmit "HELLO"):

void UART_Init() {

    SCON = 0x50; // Mode1, 8-bit UART, enable receiver

    TMOD &= 0x0F; // Clear Timer1 bits

    TMOD |= 0x20; // Timer1, Mode2 (Auto-reload for baud rate)

    TH1 = 0xFD;   // 9600 baud @ 11.0592MHz (value may vary)

    TR1 = 1;      // Start Timer1

    TI = 1;       // Ready to transmit

}

void UART_TxChar(char c) {

    SBUF = c;     // Load character

    while(!TI);   // Wait for transmission complete

    TI = 0;       // Clear flag

}

void main() {

    UART_Init();

    char msg[] = "HELLO";

    int i;

    for(i=0; msg[i]!='\0'; i++) {

        UART_TxChar(msg[i]);

    }

    while(1);

}

2.4 Interfacing Techniques and Applications

A. DAC Interfacing (e.g., DAC0800)

• Circuit Principle: 8051's parallel port (P1) provides digital input to DAC. DAC converts digital value to proportional analog current/voltage. Often requires an op-amp I/V converter to get voltage output.

• Timing Diagram: Digital inputs are latched. Conversion is generally fast (µs). Output current/voltage settles after propagation delay.

• Application Examples: Waveform generation (sine, square), analog control (motor speed, volume), calibration signals.

DiagramSEARCH: 8051 DAC0800 interfacing circuit diagram

B. ADC Interfacing (e.g., ADC0804)

• Circuit Principle: Analog signal from sensor → Signal Conditioning (amplification, filtering) → ADC input. ADC converts analog voltage to digital. 8051 reads digital output via port (e.g., P1). Control signals: CS (Chip Select), RD (Read), WR (Write/Start), INTR (Interrupt/End of Conversion).

• Working: 1. 8051 pulses WR low to start conversion. 2. ADC samples & converts. 3. INTR goes low when done. 4. 8051 pulses RD low to read data from output pins.

DiagramSEARCH: 8051 ADC0804 interfacing circuit diagram

C. Stepper Motor Interfacing

• Circuit Principle: Stepper motor has multiple coils (phases). Energizing coils in sequence causes rotation. Driver circuit (ULN2003/ Darlington array) isolates and provides current. 8051 outputs sequence to driver.

• Control Sequence (4-step unipolar): A+ → B+ → A- → B- (or similar). Timing between steps controls speed.

DiagramSEARCH: 8051 stepper motor interfacing ULN2003

D. Keyboard Interfacing

• Scanning Methods (Matrix/Row-Column):

  1. Matrix Keyboard: Rows connected to output ports, columns to input (with pull-ups).

  2. Scanning: 8051 sequentially grounds each row (outputs 0) and reads columns. A low on a column indicates key press at that row-column intersection.

• Debouncing:

  • Hardware: RC filter, Schmitt trigger.

  • Software: Delay (10-20ms) after first key detect, then re-check. If still pressed, confirm key press.

2.5 Microcontroller-Based Data Acquisition System

• System Design: Sensor → Signal Conditioning → ADC → MCU (8051) → Output/Display/Communication.

• Hardware Components:

  1. Sensor/Transducer: Converts physical parameter (temp, pressure) to electrical signal.

  2. Signal Conditioning: Amplification (op-amp), filtering (anti-aliasing), isolation.

  3. ADC: Converts conditioned analog signal to digital (e.g., ADC0804).

  4. MCU (8051): Controls ADC, reads data, processes, stores, sends to output.

  5. Output: Display (LCD), communication (UART to PC), control signal (via DAC).

• Block Diagram & Signal Flow:

  DiagramCANVAS: Block diagram showing Physical Parameter -> Sensor -> Signal Conditioning -> ADC -> 8051 (with RAM/ROM) -> Output (Display/Comm)

3.0 8096 Microcontroller

3.1 Functional Block Diagram & Superiority over 8051

DiagramSEARCH: Intel 8096 microcontroller functional block diagram

Explanation of Key Blocks:

• 16-bit CPU: 16-bit data bus, wider ALU, faster than 8-bit 8051.

• Memory: 8KB on-chip ROM, 232B on-chip RAM. Memory-Mapped I/O (I/O registers are in same address space as RAM).

• I/O Ports: 8-bit ports (P0-P4), many multiplexed with other functions (AD, ALE, etc.).

• Timers: Two 16-bit timers (Timer1, Timer2) with more modes (including PWM).

• Event Processor Array (EPA): Key Superior Feature. Dedicated hardware for high-speed I/O events (capture, compare, PWM) without CPU intervention. Enables precise real-time control.

• Serial Port: Full-duplex UART.

• ADC: On-chip 10-bit ADC (8 channels in 8096, 16 in 8097).

• Interrupt System: More sources, priority levels.

Superiority over 8051:

• 16-bit Architecture: Higher performance, larger data handling.

• Enhanced Peripherals: On-chip ADC, PWM (via EPA), more timers.

• Event Processor Array (EPA): Enables deterministic, high-speed I/O for motor control, power conversion.

• Memory-Mapped I/O: Simpler programming model.

• Higher Speed: Can operate at higher clock frequencies.

3.2 Hardware Features

• I/O Ports Structure: Most ports are multiplexed. For example, Port 0 pins can be:

  • Address/Data bus (during external memory access).

  • General-purpose I/O.

  • Analog inputs (AD0-AD7).

  • Control signals (ALE, RD, WR).

  • Mode controlled by Port Mode Special Function Register (PMSFR).

• Control and Status Register (CSR): 16-bit SFR.

  • Functions: Global interrupt enable/disable, select interrupt priority scheme (fixed/rotating), software interrupt generation.

  • Key Bits: INT_MSK (interrupt mask), INT_PEND (pending interrupts), INT_PRI (priority scheme select).

• Register Arithmetic and Logic Unit (ALU):

  • Organization: 16-bit ALU. Operates on 16-bit Register File (R0-R15) or memory.

  • Operation: All arithmetic/logic operations are register-to-register or register-memory. Memory-to-memory operations not direct. Uses accumulator (A) implicitly for some operations.

• Memory Organization & Mapping:

  • Separate Code/Data Spaces: Harvard Architecture internally.

  • Memory Map:

    • 0000H-1FFFH: On-chip ROM (8KB).

    • 2000H-20FFH: On-chip RAM (256B).

    • FF00H-FFEFH: SFRs (256 bytes).

    • External memory can be mapped anywhere via BUSCON register.

  • Memory-Mapped I/O: I/O ports and control registers are part of the same address space as RAM/ROM.

3.3 Addressing Modes (with Code Examples)

Example from Past Paper (Jun 2025):

LD R1, #05H   ; Immediate: R1 = 0x0005

LD R2, #03H   ; Immediate: R2 = 0x0003

MPY R1, R2    ; Multiply: R1 = R1 * R2 = 0x0005 * 0x0003 = 0x000F (15)

ST R1, 0200H  ; Direct: Store R1 (0x000F) to memory location 0200H.

• i) Value at 0200H: 0x000F (15).

• ii) If MPY replaced by DIV: DIV R1, R2 → R1 = R1 / R2 = 5 / 3 = 1 (integer division, quotient in R1, remainder in R2? Check specific 8096 manual: typically quotient in destination, remainder in other reg).

• iii) Overflow Risk: For MPY (16-bit * 16-bit → 32-bit result). 8096 MPY stores lower 16 bits in destination. 0x000F fits, no overflow. For larger numbers (e.g., 0xFFFF * 0xFFFF), result > 16-bit → overflow, only lower 16 bits stored. DIV no overflow (quotient always ≤ dividend).

3.4 Instruction Set Classification

1. Data Transfer: LD, ST, PUSH, POP, LDB, STB, LDM, STM.

2. Arithmetic: ADD, ADDC, SUB, SUBC, MUL (unsigned), MPY (signed), DIV.

3. Logical: AND, OR, XOR, NOT, TEST.

4. Shift/Rotate: SHL, SHR, SHLA, SHRA, RLC, RRC.

5. Branch/Jump: JMP, JBC, JBS, JNC, JNZ, CALL, RET.

6. Control: NOP, DI, EI, SINGLE (single-step), IDLE (wait).

3.5 Special Function Registers (SFRs) Overview

SFRs are memory-mapped control registers in the top 256 bytes (FF00H-FFEFH). Examples:

• PSW (Program Status Word): Flags (Carry, Zero, Overflow, etc.).

• SP (Stack Pointer): Points to top of stack in internal RAM.

• BUSCON: Bus configuration (external memory wait states).

• AD_COMMAND/AD_RESULT: ADC control and data.

• EPAx_CON/EPAx_TIME: EPA channel configuration and compare/capture time.

• P0-P4: Port data registers.

• TMOD/TCON: Timer modes and control (similar to 8051 but 16-bit).

• CSR: Control and Status Register (interrupt control).

4.0 Processor Architectures for Embedded Systems

4.1 Processor Types and Selection Criteria

Selection Criteria: Volume, Performance Requirements, Flexibility Needs, Power Budget, Cost Target, Time-to-Market.

4.2 Instruction Set Architecture (ISA) Comparison

4.3 Memory Architecture Comparison

DiagramSEARCH: Von Neumann vs Harvard architecture diagram

4.4 Advanced Processor Cores

A. ARM Processor Architecture

• RISC Features:

  • Load-Store architecture.

  • Fixed-length 32-bit (ARM state) or 16-bit (Thumb state) instructions.

  • Large register file (16 x 32-bit general-purpose).

  • Conditional execution of most instructions.

  • Highly pipelined.

• Application in Mobile Embedded: Dominant. Due to excellent performance-per-watt ratio, licensing model (ARM Holdings), and ecosystem. Used in smartphones, tablets, wearables (Cortex-A series for applications, Cortex-M for microcontrollers).

B. DSP (Digital Signal Processor) Processors

• Special Features:

  • Harvard Architecture: Separate program/data buses (often multiple).

  • Hardware Multiplier-Accumulator (MAC): Single-cycle multiply-accumulate, critical for FIR/IIR filters, FFT.

  • Zero-Overhead Looping: Dedicated hardware for loop counters, no branch penalty.

  • Special Addressing Modes: Bit-reversed, circular buffers for FFT.

  • Fixed-Point Arithmetic: Optimized for low-latency, deterministic operation.

• Role & Advantages over GPP: Specialized for compute-intensive, real-time signal processing (audio, video, telecommunications, motor control). Offers higher throughput and lower latency for DSP algorithms compared to GPP at similar clock speeds/power.

5.0 Peripherals, Interfaces, and Support Systems

5.1 Watchdog Timer (WDT)

• Purpose & Role: Improves system reliability by recovering from software hangs (infinite loops, crashes). Forces a system reset if software fails to "kick" (clear) the timer within a predefined timeout period.

• Operation Principle:

  1. Timer is enabled with a preset timeout period.

  2. Software must periodically write a specific value (or clear a flag) to a WDT control register before timeout.

  3. If timeout occurs, WDT generates a reset signal to the MCU.

  4. System restarts from known state.

• Timing Diagram: Shows periodic "kick" pulses from software. If a kick is missed, timeout pulse triggers reset.

DiagramSEARCH: Watchdog timer timing diagram

5.2 Keyboard Controller (e.g., Intel 8279)

• Functional Block Diagram & Explanation:

  DiagramSEARCH: Intel 8279 keyboard display controller block diagram

  • Keyboard Section: Scans keyboard matrix (up to 64 keys), debounces, encodes key position, stores in FIFO.

  • Display Section: Drives up to 16-digit 7-segment (or other) displays from RAM.

  • FIFO (8x8): Stores key codes (scancodes) from keyboard section. CPU reads from it.

  • Control/Status Registers: Program modes, read status.

• Modes of Operation:

  1. Scanned Keyboard Mode: Scans matrix, encodes, stores in FIFO.

  2. Scanned Display Mode: Refreshes display from display RAM.

  3. Sensor Matrix Mode: Scans external sensor array (like keyboard).

• Key-Press Processing:

  1. Scanning: 8279 sequentially grounds rows, reads columns.

  2. Debouncing: Hardware/software within 8279 (typically 2 consecutive scans).

  3. Encoding: Converts (row, col) to a scan code.

  4. FIFO: Stores scan code. CPU reads via data bus when IRQ (interrupt) is raised.

5.3 Interrupt Controllers (e.g., 8259A)

• Functional Block Diagram & Explanation:

  DiagramSEARCH: 8259A interrupt controller block diagram

  • Interrupt Request Lines (IR0-IR7): Inputs from peripheral devices.

  • Interrupt Mask Register (IMR): Masks (disables) specific IR lines.

  • Priority Resolver: Determines highest priority pending interrupt (fixed or rotating priority).

  • Interrupt Service Register (ISR): Holds bits for interrupts being serviced.

  • In-Service (IS) & Interrupt Request (IR) Pins: Output to CPU (INT), and to cascade units (CAS).

  • Cascade Buffer/Comparator: Allows cascading multiple 8259As to handle >8 interrupts (master-slave).

  • Data Buffer: For command/status/vector transfer with CPU.

• Role: Manages multiple interrupt sources for a single-CPU system. Prioritizes, masks, and presents one interrupt at a time to CPU. Provides interrupt vector (address of ISR) to CPU.

5.4 Serial Communication Standards: RS-232

• Role in Data Transmission: Standard for serial binary data exchange between DTE (Data Terminal Equipment, e.g., PC) and DCE (Data Circuit-terminating Equipment, e.g., modem). Defines electrical characteristics and signal functions.

• Main Signals & Handshaking:

  • TXD (Transmit Data): DTE → DCE.

  • RXD (Receive Data): DTE ← DCE.

  • RTS (Request To Send): DTE → DCE, asks permission to send.

  • CTS (Clear To Send): DCE → DTE, grants permission to send.

  • DTR (Data Terminal Ready): DTE → DCE, DTE is ready.

  • DSR (Data Set Ready): DCE → DTE, DCE is ready.

  • DCD (Data Carrier Detect): DCE → DTE, carrier detected (modem connection).

  • RI (Ring Indicator): DCE → DTE, ring detected.

• Handshaking: Hardware handshaking uses RTS/CTS (or DTR/DSR) to control data flow, preventing overrun. Software handshaking uses control characters (XON/XOFF) in data stream.

5.5 Real-Time Clock (RTC)

• Function & Importance: Keeps track of time of day (calendar) and date independently of main system power. Critical for:

  • Time-stamping events/data logs.

  • Scheduling tasks (alarms, wake-ups).

  • System uptime calculation.

• Basic Operation:

  • Contains a low-power oscillator (usually 32.768 kHz crystal) and battery-backed memory.

  • Maintains time/date in BCD or binary format in its registers.

  • Can generate alarm interrupts at specific times.

  • Communicates with MCU via serial interface (I²C, SPI, or parallel).

6.0 Other Microcontroller Families

6.1 16-bit PIC Microcontrollers (e.g., PIC24, dsPIC30F)

• Key Features:

  • 16-bit data path, 24-bit instruction word.

  • Modified Harvard Architecture (separate instruction/data buses, but with data access to program memory).

  • High performance (up to 40 MIPS), low power.

  • Rich peripherals: multiple UARTs, SPI, I²C, PWM, ADC, comparators.

  • Enhanced instruction set with C-friendly features.

• Typical Applications: Industrial control, motor control, consumer appliances, instrumentation requiring more performance than 8-bit.

6.2 32-bit dsPIC Microcontrollers (Digital Signal Controller)

• Key Features (DSP Capabilities):

  • 16-bit data path, but DSP-optimized instruction set.

  • Hardware barrel shifter.

  • Single-cycle MAC (Multiply-Accumulate) operation.

  • Zero-overhead looping (DO loops).

  • Modulo addressing for circular buffers.

  • Fast interrupt response (few cycles).

• Typical Applications: Digital signal processing tasks: motor control (FOC), power conversion (digital power supplies, inverters), audio processing, telecommunications. Bridges gap between MCU and dedicated DSP.