5.0 INPUT/OUTPUT (I/O) ORGANIZATION
This unit covers how the CPU communicates with external devices. Key focus areas from past papers: data transfer modes, I/O interfaces, DMA, and communication modes.
5.1 Data Transfer Modes
Three primary methods for moving data between CPU/I/O and memory:
| Mode | CPU Involvement | Key Mechanism | Advantages | Disadvantages |
|---|---|---|---|---|
| Program-Controlled I/O (Polling) | High – CPU continuously checks device status | CPU reads status register in a loop until device is ready | Simple to implement | Wastes CPU cycles; inefficient for slow devices |
| Interrupt-Driven I/O | Medium – CPU interrupted when device ready | Device sends interrupt signal; CPU executes ISR to handle transfer | CPU free to do other work between interrupts | Overhead of context save/restore; multiple interrupts can cause latency |
| Direct Memory Access (DMA) | Low – CPU involved only at start/end | DMA controller manages data transfer directly between I/O and memory | High-speed bulk transfer; minimal CPU intervention | Complex hardware; cycle stealing (DMA uses bus cycles) |
[!TIP] DMA CPU Time Calculation (Frequently asked)
The fraction of CPU time spent on DMA handling is:
$$\boxed{\text{CPU Fraction} = \frac{\text{Initiation Cycles} + \text{Completion Interrupt Cycles}}{\text{Total Cycles during Transfer Period}}}$$
Example (from Nov 2022 paper):
Data: 10 MB transferred as 2500 pages (4 KB each).
CPU: 200 MHz → Total cycles in 1 sec = $$\displaystyle 200 \times 10^6 $$ (transfer time = 1 sec at 10 MB/s).
Initiation: 1000 cycles/page → $2500 \times 1000$
Completion: 1500 cycles/page → $2500 \times 1500$
$$\text{CPU Fraction} = \frac{2500 \times 1000 + 2500 \times 1500}{200 \times 10^6} = \frac{6.25 \times 10^6}{200 \times 10^6} = 0.03125 = 3.125\%$$
Flowchart Summary:
-
Polling: CPU → Read Status → Ready? → Yes → Transfer → No → Loop
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Interrupt: CPU doing other work → Interrupt signal → Save context → ISR → Restore context → Resume
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DMA: CPU → Program DMA controller (address, count) → DMA controller → Transfer (CPU free) → Interrupt on completion
5.2 I/O Interface & Processor
I/O Interface (I/O Controller):
Hardware between CPU/IOP and I/O device. Functions:
-
Handshaking: Synchronize CPU and device speed using control signals (e.g.,
READY,BUSY). -
Buffering: Temporary storage to match speed differences (e.g., printer buffer).
-
Signal Conversion: Parallel/serial conversion, voltage level shifting, analog/digital conversion.
I/O Processor (IOP):
A dedicated processor that handles I/O tasks independently.
-
Role: Offloads I/O operations from CPU; manages multiple devices concurrently.
-
Asynchronous Transfer: IOP and CPU operate independently; communicate via shared memory or DMA.
-
Advantage: Improves system throughput; CPU executes user programs while IOP handles I/O.
[!TIP] IOP vs CPU:
- CPU: General-purpose, executes user instructions.
- IOP: Specialized for I/O, has its own instruction set (often simpler), directly controls devices.
5.3 Data Communication Modes
Directional Modes:
| Mode | Direction | Example | Usage |
|---|---|---|---|
| Simplex | One-way only | Keyboard → CPU | Unidirectional devices |
| Half-Duplex | Two-way, but not simultaneous | Walkie-talkie | Two-way communication where turn-taking is acceptable |
| Full-Duplex | Two-way simultaneously | Telephone, Ethernet | Real-time bidirectional communication |
Timing Modes:
| Mode | Synchronization | Mechanism | Typical Use |
|---|---|---|---|
| Synchronous | Clock-synchronized | Data sent in blocks with clock pulses; receiver samples at fixed intervals | High-speed buses (e.g., DDR memory) |
| Asynchronous | No shared clock | Start/stop bits per character; receiver samples at middle of bit period | Serial communication (e.g., UART, keyboard) |
[!TIP] Common Exam Question:
Differentiate half-duplex and full-duplex with examples.
- Half-Duplex: Single communication channel, alternating transmission (e.g., intercom).
- Full-Duplex: Two channels or frequency separation, simultaneous (e.g., mobile phone call).