Process Control Instrumentation (EC-504 (C)) - Unit 3 Short Notes

UNIT 3: Computer Organization & Architecture (Instrumentation Computing Aspects)

1. Fundamental Computer Structure

Von Neumann Architecture

• Components: Memory (stores data/instructions), Control Unit (CU), Arithmetic Logic Unit (ALU), Input/Output (I/O) systems.

• Stored-Program Concept: Instructions and data share the same memory and bus; program is stored as binary in memory.

• Key Limitation: Von Neumann bottleneck—sequential access to memory limits speed.

Instruction Cycle

1. Fetch: Read instruction from memory address in Program Counter (PC) into Instruction Register (IR). PC incremented.

2. Decode: Control Unit interprets opcode, determines operation and operands.

3. Execute: ALU performs operation; result stored in register/memory.

[!TIP] Common exam question: Draw flowchart showing fetch, decode, execute with register transfers (e.g., MAR ← PC, MDR ← Memory[MAR]).

Register Transfer Language (RTL) & Micro-operations

• Micro-operations: Elementary operations on registers/memory (e.g., R1 ← R2, PC ← PC + 1).

• RTL: Symbolic notation to describe micro-operations (e.g., MAR ← (PC)).

• Types: Register transfer, arithmetic, logic, shift.

Common Bus System

• Purpose: Shared pathway for data/address/control signals among registers, memory, ALU.

• Design: Multiplexers select source; tri-state buffers enable one device at a time.

• Example: 8-register system with bus; control signals SELA, SELB select inputs to ALU.

[!DIAGRAM] Search: "common bus system computer organization diagram"

2. Control Unit Design

Hardwired Control

• Design: Combinational logic (gates) generates control signals directly from instruction decoder and timing signals.

• Timing: Fixed by clock pulses; each instruction has predefined sequence.

• Advantages: Fast, no memory access.

• Disadvantages: Inflexible; difficult to modify instruction set.

Microprogrammed Control

• Concept: Control signals stored as microinstructions in control memory.

• Microinstruction: Low-level control words; each activates specific micro-operations.

• Advantages: Flexible, easier to design/debug; supports complex instructions.

• Disadvantages: Slower (extra memory access).

Micro-instruction Format

• Fields:

  • Operation field: Control signals for parallel micro-operations.

  • Address field: Next microinstruction address (for branching).

  • Next address field: Sequencing logic (e.g., CMAR ← address field).

• Vertical vs Horizontal:

  • Vertical: Compact, encoded fields (fewer bits, slower decoding).

  • Horizontal: Wide, one bit per control signal (parallelism, faster).

Microprogram Sequencer

• Block Diagram: Control Memory → Microinstruction Register → Sequencer Logic → Control Memory Address Register (CMAR).

• Operation: Fetches microinstruction, updates CMAR based on next address logic (conditional branches).

[!TIP] Exam often asks: "Explain microprogram sequencer with block diagram."

Control Signal Logic

• Derive Boolean expressions from instruction-time step table.

• Example: For instruction I1 active in T2, signal S5 = I1'·T2 + I3·T4 (where I1' means instruction decode for I1).

[!TIP] Past paper: Given table of control signals for instructions over time steps, find expressions for specific signals (e.g., S5, S6, S10).

3. Arithmetic & Logic Unit (ALU)

Multiplication Circuit

• Algorithm: Shift-and-add (e.g., Booth’s algorithm reduces steps).

• Design Challenges:

  • Speed: Sequential addition of partial products is slow.

  • Hardware: Array multipliers use many adders (fast but costly).

  • Overflow: Need wider result (2n bits for n-bit operands).

Floating-Point Representation (IEEE 754)

• Single Precision (32-bit):

  • Sign bit (1 bit)

  • Exponent (8 bits, biased by 127)

  • Mantissa (23 bits, implicit leading 1)

• Double Precision (64-bit): 1 sign, 11 exponent, 52 mantissa.

\boxed{\text{Value} = (-1)^S \times (1.M) \times 2^{(E - \text{bias})}}

Floating-Point Addition/Subtraction

1. Align exponents: Shift mantissa of smaller exponent right.

2. Add/subtract mantissas: Include sign handling.

3. Normalize result: Shift left/right to maintain 1.xxxx form; adjust exponent.

4. Round: Guard bits for precision.

5. Check overflow/underflow.

[!DIAGRAM] Search: "floating point addition alignment normalization flowchart"

ALU Design Considerations

• Integer operations: Faster, simpler circuits (carry-lookahead adders).

• Floating-point: More complex (alignment, rounding, special values like NaN/Infinity).

• Implementation: Separate integer and FP units, or unified with microcode.

4. Instruction Set Architecture

Instruction Format

• Bit allocation: Opcode field (identifies operation), address fields (source/destination), immediate/constant bits.

• Example: 16-bit instruction with 6-bit opcode, two 5-bit addresses → 64 instructions, 32 addressable locations.

\boxed{\text{Max instructions} = 2^{\text{opcode bits}}, \quad \text{Address space} = 2^{\text{address bits}}}

Addressing Modes

Instruction Encoding

• Opcode decoding: Hardwired decoder or microprogrammed.

• Address calculation: Depends on mode (e.g., direct uses address field; relative uses PC + offset).

5. Input/Output Organization

Data Transfer Modes

I/O Interface

• Role: Buffering, signal conversion, handshaking (control signals like READY, BUSY).

• Handshaking: Synchronizes CPU and I/O (e.g., STROBE and ACK signals).

I/O Processor (IOP)

• Dedicated processor handles I/O tasks asynchronously.

• Operation: CPU programs IOP with memory addresses and transfer count; IOP manages data transfer independently, interrupts CPU on completion.

Synchronous vs Asynchronous Transfer

• Synchronous: Clock-based; all devices synchronized to common clock. Simple but wastes cycles if devices vary in speed.

• Asynchronous: Handshaking signals (REQUEST, ACKNOWLEDGE); flexible for different-speed devices.

Duplex Modes

• Half-duplex: One direction at a time (e.g., walkie-talkie).

• Full-duplex: Both directions simultaneously (e.g., telephone).

[!TIP] Applications: Half-duplex for shared channels (radio); full-duplex for high-speed networks.

DMA Controller

• Block Diagram:

  CPU ↔ DMA Controller ↔ Memory ↔ I/O Device

  Registers: Command/Status, Address, Count.

• Operation:

  1. CPU programs DMA (address, count, control).

  2. DMA requests bus control (holds BUS REQUEST).

  3. CPU releases bus (acknowledges BUS GRANT).

  4. DMA transfers data directly (read/write cycles).

  5. DMA interrupts CPU on completion.

DMA Performance (CPU Overhead)

• CPU overhead = (Cycles to initiate + cycles to respond to interrupt) / (Total cycles for transfer)

• Example: Transfer N words, each takes 2 cycles (read+write). Total DMA cycles = 2N.

  CPU cycles used = C_init + C_int.

  Overhead fraction = (C_init + C_int) / (2N).

[!TIP] Past paper: Given transfer size, cycles, calculate fraction of CPU time spent.

6. Memory System

Memory Hierarchy

• Levels: Registers → Cache → Main Memory (RAM) → Secondary (Disk).

• Principle of Locality:

  • Temporal: Recently accessed data likely reused.

  • Spatial: Nearby addresses likely accessed.

• Significance: Faster, smaller memories closer to CPU reduce average access time.

Cache Memory

• Organization:

  • Cache size = Number of blocks × Block size.

  • Each block contains tag (memory address), data, valid/dirty bits.

• Address Breakdown (for n-way set associative):

  Tag | Set Index | Block Offset

  Example: 16 KB cache, 64-byte block, 4-way →

  Blocks = 16K/64 = 256; Sets = 256/4 = 64 → Index = log₂(64) = 6 bits.

Mapping Techniques

[!DIAGRAM] Search: "cache mapping direct set associative diagram"

Cache Performance

• Hit Ratio (h): Fraction of accesses found in cache.

• Miss Penalty (p): Time to fetch block from lower level (e.g., main memory).

• Average Memory Access Time (AMAT):

$$ \text{AMAT} = \text{Hit Time} + (1 - h) \times \text{Miss Penalty} $$

\boxed{\text{AMAT} = t_c + (1 - h) \times t_m}

where \( t_c \) = cache access time, \( t_m \) = main memory access time.

Memory Mapping

• Significance: Maps program’s logical addresses to physical memory; enables multiprogramming and protection.

• Effect on Execution: Determines where code/data reside; affects cache behavior and TLB hits.

Virtual Memory (Paging)

• Paging: Divide memory into fixed-size pages (e.g., 4 KB).

• Page Table: OS-maintained table mapping virtual pages to physical frames.

• Translation Lookaside Buffer (TLB): Cache for page table entries (speed up translation).

• Benefits: Larger address space than physical memory; process isolation; efficient swapping.

Fragmentation

• Internal: Wasted space within allocated block (fixed partitions).

• External: Free memory scattered in small blocks (variable partitions).

• Paging eliminates external fragmentation; internal fragmentation possible (partial page use).

7. Advanced Processor Architectures

Pipelining

• Principle: Divide instruction execution into k stages (e.g., IF, ID, EX, MEM, WB); multiple instructions in parallel.

• 4-Segment Example:

  1. Fetch (F)

  2. Decode (D)

  3. Execute (E)

  4. Write-back (W)

• Advantages: Throughput ≈ 1 / (stage time) (ideal speedup ≈ k).

• Limitations:

  • Hazards:

    • Structural: Resource conflict.

    • Data: Dependency (e.g., ADD R1, R2 followed by SUB R3, R1).

    • Control: Branches cause pipeline flush.

  • Overhead: Pipeline registers, clock skew.

[!TIP] Past paper: "Formulate four-segment pipeline" → list stages with operations.

Vector Processing

• Vector vs Scalar: Vector operates on arrays (e.g., C = A + B for all elements); scalar one element at a time.

• Architecture: Vector registers, functional units (pipelined), strided memory access.

• Applications: Scientific computing, simulations, DSP.

Multiprocessor Systems (MIMD)

• MIMD: Multiple processors execute different instructions on different data.

• Inter-Processor Communication:

  • Shared memory (with cache coherence protocols).

  • Message passing (networks, buses).

• Challenges: Synchronization, contention, scalability.

RISC Architecture

• Key Characteristics:

  • Fixed-length instructions (e.g., 32 bits).

  • Load-store design: only load/store access memory; ALU uses registers.

  • Few addressing modes.

  • Hardwired control (fast).

  • Large register set.

• Goal: Simplify instruction set for pipelining efficiency.

8. Specialized Memory & Interconnection

Associative Memory

• Content-Addressable: Access by data content, not address.

• Operation: Compare search key with all entries in parallel; return matching address(es).

• Difference from Cache:

  • Cache uses index+tag mapping; associative memory searches entire memory.

  • Associative memory used for page tables (TLB), caches use set-associative mapping.

Shared Bus Architecture

• Advantages: Simple, low cost, easy to add devices.

• Contention: Multiple masters compete → need arbitration (centralized: bus arbiter; distributed: daisy-chaining).

• Performance: Bandwidth shared; arbitration overhead.

Interconnection Structure

• For multi-processor/I/O systems:

  • Bus: Simple but limited bandwidth.

  • Crossbar: Dedicated paths, high cost.

  • Multistage (e.g., Omega network): Balance cost and performance.

Microinstruction Encoding

• Goal: Minimize control bits while preserving parallelism (mutually exclusive operations can be encoded).

• Methods:

  • Direct encoding: One bit per signal (horizontal, wide).

  • Field encoding: Group mutually exclusive signals; decode to produce control (vertical, compact).

• Example from Past Paper:

  Given microinstructions and activated signals, encode to minimize bits:

  • Group signals that never appear together (e.g., a and b in I1 and I3? Check table).

  • Use field encoding: e.g., Field 1: a,b,c → 2 bits; Field 2: d,e,f → 2 bits, etc.

  • Preserve parallelism: Signals in same microinstruction must be in different fields.

[!TIP] Past paper: "Find method of encoding microinstructions from table to minimize bits."

Solution Approach:

1. List all control signals across microinstructions.

2. Identify mutually exclusive groups (signals never active together).

3. Assign fields; each field encodes one exclusive group.

4. Calculate bits: ceil(log₂(group size)) per field.

5. Total bits = sum of field bits.