Process Control Instrumentation (EC-504 (C)) - Unit 1 Short Notes

1.0 Fundamental Computer Architecture

Von Neumann Model

• Components:

  • Memory: Stores both instructions and data uniformly.

  • Control Unit (CU): Fetches, decodes, and controls instruction execution.

  • Arithmetic Logic Unit (ALU): Performs arithmetic/logic operations.

  • Input/Output: Interfaces with external devices.

• Stored-program concept: Instructions and data reside in the same memory; program counter (PC) sequentially fetches instructions.

• Instruction/Data Handling: CU fetches instruction via PC → MAR → memory → MDR → IR. Data is moved between memory and registers via a common bus. ALU operates on data from registers.

[!TIP] Exam focus: Diagram with labeled components. Emphasize single memory for instructions/data and sequential execution.

Common Bus System Architecture

• Structure: Shared set of lines (bus) connecting registers, memory, and ALU. Multiplexers select source for bus; decoders select destination.

• Operation: At each clock cycle, one source drives the bus; control signals enable one destination to receive data. Enables efficient data transfer among units.

• Example: In a basic computer, registers (PC, IR, MAR, MDR, AC) and memory are connected via a common bus for read/write operations.

Basic Functional Units and Interconnection

• CPU: CU (decodes/controls) + ALU (computes).

• Registers: Fast storage inside CPU (PC, IR, MAR, MDR, general-purpose).

• Memory: Main storage (RAM) for instructions/data.

• Interconnection: All units linked by address bus (for memory locations), data bus (for data transfer), and control bus (for signals like read/write).

2.0 Instruction Execution and Control

Instruction Cycle Phases

1. Fetch: PC → MAR → memory read → MDR → IR; PC ← PC + 1.

2. Decode: CU decodes opcode in IR, determines operation and addressing mode.

3. Execute: CU generates control signals to perform operation (e.g., ALU action, memory access, I/O).

4. Indirect (if needed): Fetch operand address from memory.

5. Interrupt (if needed): Handle interrupt before continuing.

[!TIP] Flowchart: Fetch → Decode → Execute → (Indirect?) → (Interrupt?) → repeat. Past papers often ask for flowchart with all cycles.

Instruction Format Design

• Fields:

  • Opcode: Specifies operation (e.g., ADD, LOAD).

  • Address fields: Locations of operands (1, 2, or 3 addresses).

  • Indirect address bit (I): 0 = direct, 1 = indirect addressing.

• Capacity Calculation:

  • If instruction length = $L$ bits, opcode = $o$ bits, address bits = $a$ bits per address.

  • Number of distinct instructions = $$\displaystyle 2^o $$.

  • Number of addressable memory locations = $$\displaystyle 2^a $$ (if address field directly maps to memory).

  • Example: 16-bit instruction, 6-bit opcode, 10-bit address → $$\displaystyle 2^6 = 64 $$ instructions, $$\displaystyle 2^{10} = 1024 $$ addresses.

Addressing Modes

[!TIP] Past exams require examples. Note memory accesses: immediate/register = 0, direct/register-indirect = 1, indirect = 2.

Micro-operations and Register Transfer Language (RTL)

• Micro-operations: Elementary operations on registers.

  • Transfer: $$\displaystyle R1 \leftarrow R2 $$

  • Arithmetic: $$\displaystyle R1 \leftarrow R1 + R2 $$

  • Logic: $$\displaystyle R1 \leftarrow R1 \land R2 $$

  • Shift: $$\displaystyle R1 \leftarrow R1 \ll 1 $$

• RTL Notation: Symbolic representation of control signals and data movement.

  • Example: Fetch cycle: $$\displaystyle MAR \leftarrow PC $$, $$\displaystyle MDR \leftarrow M[MAR] $$, $$\displaystyle IR \leftarrow MDR $$, $$\displaystyle PC \leftarrow PC + 1 $$.

3.0 Control Unit Design

Hardwired Control Unit

• Design: Combinational logic (gates) generates control signals directly from instruction decoder and timing (clock) signals.

• Operation: Instruction register decoded → control signals activated based on current state (time step T1, T2, ...).

• Advantages: Fast (no memory access), efficient.

• Disadvantages: Inflexible, complex wiring for large ISAs.

• Boolean Expressions: From micro-operation table, derive for each control signal. E.g., $$\displaystyle S5 = I_1 T1 + I_2 T1 + I_3 T1 + I_4 T1 $$ (from past paper).

[!TIP] Past paper: Given control signal table over time steps for instructions, derive Boolean expressions. Use sum-of-products.

Microprogrammed Control Unit

• Concepts:

  • Control Memory (CM): Stores microinstructions (microprogram).

  • Each machine instruction → sequence of microinstructions.

  • Microprogram Sequencer: Generates address of next microinstruction.

• Advantages: Flexible (easy to modify ISA), simpler design for complex instructions.

• Disadvantages: Slower (extra CM access), larger area.

Micro-instruction Format

• Horizontal:

  • Many bits (one per control signal).

  • High parallelism (multiple operations per cycle).

  • Large CM size.

• Vertical:

  • Encoded fields (log₂(n) bits for n signals).

  • Smaller CM, but requires decoding → slower.

  • Trade-off: Field encoding preserves some parallelism while reducing bits.

• Example: Horizontal: S1 S2 S3 ... S20 (20 bits). Vertical: F1 F2 F3 where each field selects one of several operations.

Microprogram Sequencer

• Role: Generates next microinstruction address.

• Operations:

  • Increment: Next sequential address (common).

  • Branch: Conditional/unconditional jump based on status bits (e.g., zero flag).

  • Subroutine call/return: Push/pop return address.

• Implementation: Often uses a counter with multiplexers for branch addresses and a stack for returns.

Control Signal Generation

• From micro-operation table: For each microinstruction, list active control signals.

• Derive minimal Boolean expressions using Karnaugh maps or Quine-McCluskey to minimize logic.

• Example: Given table with microinstructions I1–I6 and signals a–j, group signals to minimize bits while preserving parallelism.

4.0 Arithmetic and Logic Unit (ALU)

Design of Arithmetic Circuits

• Half-Adder:

  • Inputs: A, B; Outputs: Sum, Carry.

  • Truth table:

    | A | B | Sum | Carry | |---|---|-----|-------| | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 1 |

  • Equations: $$\displaystyle Sum = A \oplus B $$, $$\displaystyle Carry = A \land B $$.

• Full-Adder:

  • Inputs: A, B, $$\displaystyle C_{in} $$; Outputs: Sum, $$\displaystyle C_{out} $$.

  • Equations: $$\displaystyle Sum = A \oplus B \oplus C_{in} $$, $$\displaystyle C_{out} = (A \land B) \lor (C_{in} \land (A \oplus B)) $$.

• Multi-bit Adders:

  • Ripple-carry: Connect full-adders in series; slow due to carry propagation.

  • Carry-lookahead: Generate carries in parallel; faster but more complex.

• Multiplication:

  • Algorithm: Add-shift (for each bit of multiplier, add multiplicand if bit=1, then shift).

  • Challenges:

    • Partial products: Many additions needed.

    • Speed: Carry propagation in adders.

    • Area: Large circuits for multi-bit.

  • Circuits: Array multiplier (grid of adders), Booth’s algorithm (reduce partial products).

Floating-Point Representation and Operations

• IEEE 754 Standard:

  • Single precision (32-bit): 1 sign bit, 8 exponent bits (bias 127), 23 fraction bits (with implicit leading 1).

  • Double precision (64-bit): 1 sign, 11 exponent (bias 1023), 52 fraction.

  • Value: $$\displaystyle (-1)^s \times 1.f \times 2^{(e - bias)} $$ (normalized).

• Floating-Point Addition/Subtraction:

  1. Align exponents: Shift mantissa of smaller exponent right until exponents equal.

  2. Add/subtract mantissas: Include hidden bit.

  3. Normalize: Shift result left/right to have leading 1; adjust exponent.

  4. Round: Apply rounding mode (e.g., round to nearest).

  5. Check overflow/underflow: Exponent too large/small.

• Flowchart:

  • Start → Compare exponents → Shift smaller mantissa → Add/subtract → Normalize → Round → Check exceptions → End.

Decimal and Floating-Point Arithmetic in ALU

• Decimal (BCD): Each decimal digit in 4 bits. Addition: binary add then adjust if sum >9 (add 6). Requires extra correction logic.

• Floating-point: Often handled by separate FPU; ALU may have special circuits for alignment, normalization, rounding.

5.0 Input/Output Systems

Data Transfer Modes

[!TIP] Compare: CPU overhead highest in polled, lower in interrupt, lowest in DMA. DMA best for large blocks.

I/O Interface and I/O Processor

• I/O Interface:

  • Converts electrical signals, handles timing, provides handshaking signals (READY, ACK).

  • Contains data buffer, status/control registers.

  • Enables asynchronous communication between CPU and slow I/O.

• I/O Processor (IOP):

  • Dedicated processor for I/O tasks.

  • Implements high-level protocols (e.g., SCSI, USB), error checking, buffering.

  • Offloads CPU; can perform DMA and interrupt handling autonomously.

Asynchronous vs. Synchronous Data Transfer

• Synchronous:

  • Data transfer synchronized by a global clock.

  • All devices operate on clock edges; fixed timing.

  • Simple but requires all devices to support same clock rate.

• Asynchronous:

  • Handshaking signals (e.g., STROBE, ACKNOWLEDGE) control transfer.

  • No common clock; devices operate at own speeds.

  • More flexible; used for I/O with varying speeds.

DMA Controller

• Organization:

  • Registers: Command (start/stop), Status (busy, error), Memory Address (source/dest), Byte Count.

  • Control logic: Manages bus arbitration, data transfer.

  • Interface to system bus and I/O device.

• Interfacing:

  • Connected to address, data, control buses.

  • Requests bus control via HOLD signal; CPU acknowledges with HLDA.

• Transfer Process:

  1. CPU programs DMA: sets address, count, direction, starts transfer.

  2. DMA requests bus (HOLD).

  3. CPU releases bus (HLDA); DMA becomes bus master.

  4. DMA transfers data block (word-by-word or burst).

  5. DMA releases bus, interrupts CPU (INT) on completion.

• CPU Overhead Calculation:

  • Total transfer time: $$\displaystyle T_{total} = \frac{S}{B} $$ where $S$ = data size, $B$ = bus bandwidth.

  • CPU cycles used: $$\displaystyle C_{init} + C_{int} $$ (initiation + interrupt handling).

  • CPU time fraction: $$\displaystyle \frac{C_{init} + C_{int}}{f_{cpu} \times T_{total}} $$ where $$\displaystyle f_{cpu} $$ = CPU clock frequency.

  • Example from past paper: 10 MB/s transfer, 100 MB/s bus, 2500 pages × 4 KB, CPU 200 MHz, 1000 cycles init, 1500 cycles interrupt → calculate fraction.

[!TIP] Past exam: Calculate CPU overhead. Remember: DMA transfer time = data size / bus bandwidth. CPU cycles during transfer = transfer time × CPU clock rate.

Duplex Modes

• Half-duplex: Data flows in both directions but not simultaneously (e.g., walkie-talkie, early Ethernet).

• Full-duplex: Simultaneous two-way communication (e.g., telephone, modern Ethernet).

• Scenarios:

  • Half-duplex: Shared medium, cost-sensitive, low traffic.

  • Full-duplex: Dedicated links, high performance, full bandwidth utilization.

6.0 Memory Systems

Memory Hierarchy

• Levels (fastest to slowest):

  1. Registers (CPU internal)

  2. Cache (SRAM)

  3. Main Memory (DRAM)

  4. Secondary Storage (disk, SSD)

• Significance:

  • Locality: Temporal (reuse) and spatial (nearby) locality exploited.

  • Trade-off: Speed vs. cost vs. capacity. Faster memory is smaller and costlier.

  • Goal: Achieve average access time close to fastest level at cost of slower levels.

Cache Memory

• Organization:

  • Cache size = number of blocks × block size (bytes).

  • Block: Fixed-size unit transferred between cache and memory.

  • Example: 8 kB cache, 64-byte block → $$\displaystyle 8 \times 1024 / 64 = 128 $$ blocks.

• Mapping Techniques:

  • Direct-mapped:

    • Each memory block maps to exactly one cache line: index = block address mod number of lines.

    • Simple but high conflict misses.

    • Tag stored per line; valid bit.

  • Associative:

    • Memory block can map to any cache line.

    • Flexible, low conflict misses, but requires searching all tags (parallel comparators) → expensive.

  • Set-associative (e.g., 2-way, 4-way):

    • Cache divided into sets; each block maps to a set (index = block address mod number of sets).

    • Within set, block can go anywhere (associative).

    • Compromise: fewer tags to search than fully associative, less conflict than direct.

• Performance Metrics:

  • Hit ratio (h): Fraction of accesses found in cache.

  • Miss penalty (p): Time to fetch block from lower level (including transfer + any overhead).

  • Average Memory Access Time (AMAT):

$$\text{AMAT} = \text{Hit time} + \text{Miss rate} \times \text{Miss penalty}$$

\boxed{\text{AMAT} = t_c + (1 - h) \times t_m}

where $$\displaystyle t_c $$ = cache access time, $$\displaystyle t_m $$ = memory access time on a miss (includes transfer).

• Example: $$\displaystyle t_c = 100 $$ ns, $$\displaystyle h = 0.9 $$, $$\displaystyle t_m = 1000 $$ ns → AMAT = 100 + 0.1×1000 = 200 ns.

• Replacement Policies:

  • LRU (Least Recently Used): Replace block not used for longest time. Good temporal locality.

  • FIFO (First-In First-Out): Replace oldest block.

  • Random: Randomly select; simple, sometimes effective.

[!TIP] Cache miss analysis: Given memory access sequence, cache size, block size, compute hits/misses. For direct-mapped: index = address mod number of blocks (if 1-word blocks). Track tags and valid bits.

Virtual Memory

• Paging:

  • Virtual address space divided into fixed-size pages.

  • Physical memory divided into frames (same size as page).

  • Page table maps virtual page number → frame number.

  • Offset within page unchanged.

  • Benefits: Allows programs larger than physical memory, memory protection, sharing.

  • Implementation:

    • Page table stored in memory; accessed via TLB (Translation Lookaside Buffer) for speed.

    • Hierarchical, hashed, or inverted page tables for large spaces.

• Segmentation:

  • Variable-size segments (code, data, stack).

  • Segment table maps segment number → base address + limit.

  • Benefits: Natural program structure, protection, sharing.

  • Drawbacks: External fragmentation.

• Fragmentation:

  • Internal: Paging: last page may have unused space (fixed block size).

  • External: Segmentation: free memory scattered in small holes.

• TLB: Fast associative cache for page table entries; reduces translation overhead.

Associative Memory

• Content-Addressable Memory (CAM):

  • Access by data content rather than address.

  • All entries searched in parallel; returns address if match.

• Difference from Cache:

  • Cache is a specialized associative memory for address translation (tags + data).

  • CAM used for fast lookups (e.g., TLB, router tables, databases).

  • Cache typically set-associative; CAM often fully associative.

7.0 Advanced Processor Concepts

Instruction Pipelining

• Pipeline Segments (typical 5-stage):

  1. IF (Instruction Fetch): Get instruction from memory.

  2. ID (Instruction Decode): Decode opcode, read registers.

  3. EX (Execute): ALU operation, address calculation.

  4. MEM (Memory Access): Read/write data memory.

  5. WB (Write Back): Write result to register.

• Operation: Each stage works on different instruction simultaneously; pipeline registers between stages.

• Advantages:

  • Increased throughput: ideally one instruction completed per cycle after pipeline fill.

  • Better resource utilization.

• Limitations:

  • Hazards:

    • Structural: Resource conflict (e.g., two instructions need memory in same cycle).

    • Data: Dependency (e.g., instruction 2 needs result of instruction 1). Requires forwarding or stalls.

    • Control: Branches cause pipeline to fetch wrong instructions. Branch prediction, delayed slots.

  • Stalls (Bubbles): Inserted to resolve hazards; reduce throughput.

  • Pipeline overhead: Pipeline registers add latency to individual instruction.

• Throughput: Limited by slowest stage; pipeline depth increases complexity and hazard probability.

[!TIP] Past papers ask for 4-segment pipeline. Example: F, D, E, W. Explain each stage and hazards.

Vector Processing and Parallel Architectures

• Vector Processors:

  • Process arrays (vectors) with single instruction.

  • Example: ADD V1, V2, V3 adds corresponding elements of three vectors.

  • High memory bandwidth, pipelined ALU for vector operations.

  • Applications: Scientific computing, graphics, signal processing.

• Scalar Processing: One operation per instruction on single data items.

• Flynn’s Taxonomy:

  • SISD: Single Instruction, Single Data (traditional sequential).

  • SIMD: Single Instruction, Multiple Data (vector, MMX, SSE, GPU cores).

  • MISD: Multiple Instruction, Single Data (rare, e.g., some fault-tolerant systems).

  • MIMD: Multiple Instruction, Multiple Data (multiprocessors, clusters). Each processor executes independent instruction streams.

Inter-processor Communication

• Shared Memory:

  • Processors access common physical memory.

  • Communication via reading/writing shared variables.

  • Challenges: Cache coherence (MESI protocol), synchronization (locks, semaphores).

• Message Passing:

  • Processors send explicit messages over network (e.g., bus, interconnect).

  • No shared memory; each processor has private memory.

  • Used in distributed systems, clusters.

  • Challenges: Latency, overhead, message routing.

8.0 Performance Analysis and Case Studies

Average Memory Access Time (AMAT)

• Formula:

$$\text{AMAT} = t_c + (1 - h) \times t_m$$

where $$\displaystyle t_c $$ = cache access time, $h$ = hit ratio, $$\displaystyle t_m $$ = miss penalty (time to access next level + transfer).

• For multilevel caches:

$$\text{AMAT} = t_{c1} + (1 - h_1) \times (t_{c2} + (1 - h_2) \times t_{mem})$$

• Given values: Compute directly. Example from past paper: cache hit time 100 ns, main memory 1000 ns, hit ratio 0.9 → AMAT = 100 + 0.1×1000 = 200 ns.

Cache Miss Analysis

• Given: Memory access sequence, cache size, block size, mapping type.

• Steps:

  1. Determine number of blocks: $$\displaystyle N = \text{cache size} / \text{block size} $$.

  2. For each address:

     • Convert to block address (if byte-addressable, divide by block size).

     • For direct-mapped: index = block address mod $N$; compare tag.

     • For set-associative: index = block address mod number of sets; search within set.

     • For fully associative: search all tags.

  3. Apply replacement policy (LRU, FIFO) on misses.

• Example from past paper: 4 cache blocks, 1-word blocks, addresses: 433, 435, 536, 535, 443, 444, 551, 538, 539, 553 (hex? but given as decimal likely). Compute hits/misses for direct, 2-way set-assoc (LRU), fully assoc (FIFO).

  • Direct-mapped: index = address mod 4. Track tags.

  • 2-way set-assoc: 2 blocks per set → 2 sets; index = address mod 2; each set has 2 blocks (LRU within set).

  • Fully assoc: 4 blocks total; FIFO replacement.

Bandwidth and Throughput Calculations

• I/O Bus Bandwidth:

  • Bandwidth = clock frequency × bits per transfer / 8 (bytes/s).

  • Example: 33 MHz, 32 bits → $$\displaystyle 33 \times 10^6 \times 4 = 132 $$ MB/s.

• DMA Transfer Time:

  • Transfer size $S$ bytes, bus bandwidth $B$ bytes/s → $$\displaystyle T_{transfer} = S / B $$.

• CPU Overhead:

  • CPU cycles for initiation: $$\displaystyle C_{init} $$.

  • CPU cycles for interrupt handling: $$\displaystyle C_{int} $$.

  • Total CPU cycles during transfer: $$\displaystyle T_{transfer} \times f_{cpu} $$.

  • Fraction of CPU time: $$\displaystyle \frac{C_{init} + C_{int}}{T_{transfer} \times f_{cpu}} $$.

  • Example from past paper: 10 MB/s device, 100 MB/s bus, 2500 pages × 4 KB = 10 MB, CPU 200 MHz, 1000 cycles init, 1500 cycles interrupt.

    • $$\displaystyle T_{transfer} = 10 \text{ MB} / 100 \text{ MB/s} = 0.1 $$ s.

    • Total CPU cycles = $$\displaystyle 0.1 \times 200 \times 10^6 = 20 \times 10^6 $$ cycles.

    • CPU cycles used = 1000 + 1500 = 2500.

    • Fraction = $$\displaystyle 2500 / 20 \times 10^6 = 0.000125 = 0.0125\% $$.

Instruction Encoding and Design

• Bit Allocation:

  • Instruction length $L$ bits.

  • Opcode: $o$ bits → $$\displaystyle 2^o $$ instructions.

  • Address fields: $$\displaystyle a_1, a_2, ... $$ bits each.

  • If direct addressing, addressable memory locations = $$\displaystyle 2^{a} $$ (if address field size = $a$).

  • But total memory size may be larger; address field may be part of larger address (e.g., with base/displacement).

• Example: 16-bit instruction, 6-bit opcode, two 5-bit addresses → 64 instructions, each address field can address $$\displaystyle 2^5 = 32 $$ locations. If memory is larger, need multiple instructions or extended addressing.

9.0 Special Topics and Applications

RISC vs. CISC

• CISC (Complex Instruction Set Computer):

  • Large number of instructions (hundreds), variable length.

  • Many addressing modes, complex operations (e.g., string manipulate).

  • Microprogrammed control common.

  • Goals: Reduce program size, simplify compiler.

  • Example: x86.

• RISC (Reduced Instruction Set Computer):

  • Small set of simple instructions (tens), fixed length.

  • Few addressing modes (typically register-direct, immediate).

  • Hardwired control, pipelined efficiently.

  • Goals: Maximize instruction throughput, simplify hardware.

  • Example: ARM, MIPS, RISC-V.

• Comparison: RISC favors hardware simplicity and pipelining; CISC favors software density. Modern processors blend both (CISC with RISC core).

Memory Mapping

• Concept: Assigning specific memory address ranges to I/O devices (memory-mapped I/O) or to physical memory.

• Significance:

  • Allows CPU to access I/O using regular load/store instructions.

  • Simplifies programming and unification of memory/I/O space.

  • Enables DMA to access I/O buffers as memory.

• Effect on Program Execution:

  • I/O operations become memory accesses; must ensure addresses don’t conflict with physical memory.

  • Requires careful address allocation in system design.

  • May need protection mechanisms to prevent user programs from accessing I/O addresses.

Skin Depth and Electromagnetic Waves (Excluded)

• Not part of Process Control Instrumentation syllabus per past papers; only appeared in separate Electromagnetic Theory paper. Exclude.

Poynting Vector and Power Flow (Excluded)

• Similarly excluded; not in Computer Organization papers.