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BT-104 · Basic Electrical & Electronics Engineering/Quick Revision Short Notes

Basic Electrical & Electronics Engineering (BT-104) - Unit 5 Short Notes

How unit 5 is examined

Digital basics (number systems, gates, adders, flip-flops), then the diode and the BJT. Marks sit in the CE and CB characteristics, the R-S and J-K flip-flops, logic gates and the diode V-I curve.

Number systems & Their conversion used in digital electronics

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Definition. A number system of base $r$ uses $r$ digits, and each digit has a place value that is a power of $r$; digital electronics uses binary (2), octal (8), decimal (10) and hexadecimal (16).

Key points.

  1. Decimal to another base: divide the integer part repeatedly by the base and read the remainders upward; multiply the fraction repeatedly by the base and read the carried-out integers downward.
  2. Octal to binary: replace each octal digit by its 3-bit code; hex to binary: replace each hex digit by its 4-bit code (A=1010, B=1011, C=1100).
  3. Hex to octal: convert to binary first, then regroup in 3 bits from the binary point outward, padding zeros at the ends.
  4. To find an unknown base, expand the number as powers of $x$ and equate it to the decimal value.

Example (Dec 2024).

Part Working Answer
i) $(257)_8$ 2=010, 5=101, 7=111 $(10101111)_2$
ii) $(21.625)_{10}$ 21 = 2×8+5 gives 25; 0.625×8 = 5.0 gives .5 $(25.5)_8$
iii) $(BC.2)_{16}$ 1011 1100 . 0010, regroup: 010 111 100 . 001 000 $(274.1)_8$
iv) $(33)_{10}=(201)_x$ $2x^2+0x+1=33$, $x^2=16$ $x=4$

Answer frame. Show each conversion as its own line of working, regroup in 3s for octal, and state the answer with the base as a subscript.

Asked: [7 marks] (Dec 2024) Solve for $x$: i) $(257)_8=(x)_2$ ii) $(21.625)_{10}=(x)_8$ iii) $(BC.2)_{16}=(x)_8$ iv) $(33)_{10}=(201)_x$

De Morgan's theorem

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Definition. ==De Morgan's theorems state that the complement of a sum is the product of the complements, $\overline{A+B}=\bar A\cdot\bar B$, and the complement of a product is the sum of the complements, $\overline{A\cdot B}=\bar A+\bar B$.==

Key points.

  1. The first theorem says a NOR gate equals a bubbled-input AND gate; the second says a NAND gate equals a bubbled-input OR gate.
  2. To apply it, break the bar over the expression and change the operator (AND to OR, OR to AND).
  3. It extends to any number of variables and is used to convert circuits to NAND-only or NOR-only form.
  4. Truth-table proof: for $A=0,B=1$, $\overline{A+B}=0$ and $\bar A\bar B=1\cdot0=0$; the two columns match for all four rows.

Asked: [14 marks] (Nov 2022, Jun 2023, Dec 2023) Short note on De Morgan's theorem (options in "any two" notes; state both theorems with truth-table verification)

Logic Gates

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Definition. <mark>A logic gate is a digital circuit with one or more inputs and a single output that follows a Boolean rule; AND, OR and NOT are basic gates, and NAND and NOR are universal gates.</mark>

Key points.

  1. AND gives 1 only when all inputs are 1 ($Y=A\cdot B$); OR gives 1 when any input is 1 ($Y=A+B$).
  2. NOT inverts its single input ($Y=\bar A$).
  3. NAND is AND followed by NOT ($Y=\overline{AB}$) and NOR is OR followed by NOT ($Y=\overline{A+B}$).
  4. NAND and NOR are universal because any other gate can be built from either one alone.
  5. XOR gives 1 when the inputs differ ($Y=A\oplus B$); XNOR gives 1 when they are equal.
  6. Symbols: AND has a D-shaped body, OR a curved-back body, and a small bubble on the output marks inversion (NOT, NAND, NOR).

Truth table.

A B AND OR NAND NOR XOR NOT A
0 0 0 0 1 1 0 1
0 1 0 1 1 0 1 1
1 0 0 1 1 0 1 0
1 1 1 1 0 0 0 0

Answer frame. Open with the definition; draw the symbol of each of AND, OR, NOT, NAND and NOR beside its Boolean expression; give the combined truth table; close by saying NAND and NOR are universal.

Pitfall: NAND and NOR are the universal gates; do not call AND or OR universal.

Asked: [14 marks] (Jun 2025) Write short notes on any two: i) Logic gates ii) R-S flip flop iii) Compare electric and magnetic circuit iv) B-H curve

Half and full adder circuits

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Definition. <mark>An adder is a combinational circuit that adds binary numbers; a half adder adds two bits, and a full adder adds two bits plus a carry-in.</mark>

Key points.

  1. Half adder: $Sum=A\oplus B$ and $Carry=A\cdot B$, built from one XOR and one AND gate.
  2. Full adder has inputs $A$, $B$, $C_{in}$ and outputs $Sum$ and $C_{out}$.
  3. $Sum=A\oplus B\oplus C_{in}$ and $C_{out}=AB+C_{in}(A\oplus B)$.
  4. A full adder is two half adders plus an OR gate: the first adds $A,B$; the second adds its sum to $C_{in}$; the two carries are ORed.

Truth table (full adder).

A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u5-01" viewBox="0 0 553 295" width="553" height="295" role="img" aria-label="Full adder from two half adders. X1, X2 are XOR gates; A1, A2 are AND gates; OR combines the carries."><style>#dsfig-u5-01 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u5-01 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u5-01 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u5-01 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u5-01 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u5-01 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u5-01 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u5-01 .t{fill:#16181D;font-weight:500}#dsfig-u5-01 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u5-01 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u5-01 .dot{fill:#16181D}#dsfig-u5-01 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u5-01 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u5-01 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u5-01 .ah{fill:#454C5A}#dsfig-u5-01 .ah.hi{fill:#2340B8}#dsfig-u5-01 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u5-01 .wl .t{font-size:12px;font-weight:700}#dsfig-u5-01 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u5-01 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u5-01 .e{stroke:#B1B7C3}html.dark #dsfig-u5-01 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u5-01 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u5-01 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u5-01 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u5-01 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u5-01 .t{fill:#E6E8ED}html.dark #dsfig-u5-01 .t.inv{fill:#0F1115}html.dark #dsfig-u5-01 .kd{stroke:#E6E8ED}html.dark #dsfig-u5-01 .dot{fill:#E6E8ED}html.dark #dsfig-u5-01 .ann{fill:#8FA3FF}html.dark #dsfig-u5-01 .lbl{fill:#858D9C}html.dark #dsfig-u5-01 .ptr{fill:#8FA3FF}html.dark #dsfig-u5-01 .ah{fill:#B1B7C3}html.dark #dsfig-u5-01 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u5-01 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u5-01 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u5-01 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah13" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh13" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M58,46 L149.1,76.4" marker-end="url(#ah13)"/><path class="e" d="M58,120 L149.1,89.6" marker-end="url(#ah13)"/><path class="e" d="M52.6,54.2 L155.1,170.5" marker-end="url(#ah13)"/><path class="e" d="M57.2,134 L150,177.3" marker-end="url(#ah13)"/><path class="e" d="M187,89 L278.1,119.4" marker-end="url(#ah13)"/><path class="e" d="M57,246.5 L279.2,135.4" marker-end="url(#ah13)"/><path class="e" d="M181.6,97.2 L284.1,213.5" marker-end="url(#ah13)"/><path class="e" d="M58.9,253.1 L277.1,231.3" marker-end="url(#ah13)"/><path class="e" d="M317,126 L492,126" marker-end="url(#ah13)"/><path class="e" d="M187.9,188.1 L406.1,209.9" marker-end="url(#ah13)"/><path class="e" d="M316.8,226.7 L406.2,214.8" marker-end="url(#ah13)"/><path class="e" d="M444,220.5 L494.2,245.6" marker-end="url(#ah13)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">A</text><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">B</text><circle class="n" cx="40" cy="255" r="18"/><text class="t" x="40" y="255" dy=".35em" text-anchor="middle">Ci</text><circle class="n" cx="169" cy="83" r="18"/><text class="t" x="169" y="83" dy=".35em" text-anchor="middle">X1</text><circle class="n" cx="298" cy="126" r="18"/><text class="t" x="298" y="126" dy=".35em" text-anchor="middle">X2</text><circle class="n" cx="169" cy="186.2" r="18"/><text class="t" x="169" y="186.2" dy=".35em" text-anchor="middle">A1</text><circle class="n" cx="298" cy="229.2" r="18"/><text class="t" x="298" y="229.2" dy=".35em" text-anchor="middle">A2</text><circle class="n" cx="427" cy="212" r="18"/><text class="t" x="427" y="212" dy=".35em" text-anchor="middle">OR</text><circle class="n" cx="513" cy="126" r="18"/><text class="t" x="513" y="126" dy=".35em" text-anchor="middle">Sum</text><circle class="n" cx="513" cy="255" r="18"/><text class="t" x="513" y="255" dy=".35em" text-anchor="middle">Co</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Full adder from two half adders. X1, X2 are XOR gates; A1, A2 are AND gates; OR combines the carries.</figcaption></figure>

Answer frame. Open with the definition of an adder; draw the two-half-adder circuit; give the truth table and both equations; close with the two-half-adders-plus-OR statement.

Asked: [7 marks] (Dec 2023) What do you understand by Adder circuit? Draw and explain the working principle of full adder circuit.

R-S flip flop

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Definition. <mark>An R-S (Set-Reset) flip-flop is a bistable memory element with two inputs, S and R, and complementary outputs $Q$ and $\bar Q$, that stores one bit.</mark>

Key points.

  1. It is built from two cross-coupled NOR (or NAND) gates, the output of each feeding an input of the other.
  2. S=0, R=0 is the no-change (memory) state: the output holds its previous value $Q_n$.
  3. S=1, R=0 sets the flip-flop, giving $Q=1$; S=0, R=1 resets it, giving $Q=0$.
  4. S=1, R=1 is invalid for NOR: both outputs go to 0, violating $Q=\bar Q'$, and the final state is unpredictable when both inputs return to 0 (race condition).
  5. A NAND latch has active-low inputs, so its invalid state is S=R=0.
  6. It is the basic memory cell of sequential circuits; a clocked version changes state only on the clock pulse.

Truth table (NOR latch).

S R $Q_{n+1}$ State
0 0 $Q_n$ No change
0 1 0 Reset
1 0 1 Set
1 1 ? Invalid

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u5-02" viewBox="0 0 424 252" width="424" height="252" role="img" aria-label="R-S flip-flop from two cross-coupled NOR gates N1, N2; Q and Qb (Q bar) are the outputs."><style>#dsfig-u5-02 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u5-02 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u5-02 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u5-02 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u5-02 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u5-02 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u5-02 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u5-02 .t{fill:#16181D;font-weight:500}#dsfig-u5-02 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u5-02 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u5-02 .dot{fill:#16181D}#dsfig-u5-02 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u5-02 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u5-02 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u5-02 .ah{fill:#454C5A}#dsfig-u5-02 .ah.hi{fill:#2340B8}#dsfig-u5-02 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u5-02 .wl .t{font-size:12px;font-weight:700}#dsfig-u5-02 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u5-02 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u5-02 .e{stroke:#B1B7C3}html.dark #dsfig-u5-02 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u5-02 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u5-02 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u5-02 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u5-02 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u5-02 .t{fill:#E6E8ED}html.dark #dsfig-u5-02 .t.inv{fill:#0F1115}html.dark #dsfig-u5-02 .kd{stroke:#E6E8ED}html.dark #dsfig-u5-02 .dot{fill:#E6E8ED}html.dark #dsfig-u5-02 .ann{fill:#8FA3FF}html.dark #dsfig-u5-02 .lbl{fill:#858D9C}html.dark #dsfig-u5-02 .ptr{fill:#8FA3FF}html.dark #dsfig-u5-02 .ah{fill:#B1B7C3}html.dark #dsfig-u5-02 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u5-02 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u5-02 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u5-02 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah14" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh14" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L191,40" marker-end="url(#ah14)"/><path class="e" d="M59,212 L191,212" marker-end="url(#ah14)"/><path class="e" d="M231,40 L363,40" marker-end="url(#ah14)"/><path class="e" d="M231,212 L363,212" marker-end="url(#ah14)"/><path class="e" d="M205.4,57.8 Q180,126 204.7,192.3" marker-end="url(#ah14)"/><path class="e" d="M218.6,194.2 Q244,126 219.3,59.7" marker-end="url(#ah14)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">R</text><circle class="n" cx="40" cy="212" r="18"/><text class="t" x="40" y="212" dy=".35em" text-anchor="middle">S</text><circle class="n" cx="212" cy="40" r="18"/><text class="t" x="212" y="40" dy=".35em" text-anchor="middle">N1</text><circle class="n" cx="212" cy="212" r="18"/><text class="t" x="212" y="212" dy=".35em" text-anchor="middle">N2</text><circle class="n" cx="384" cy="40" r="18"/><text class="t" x="384" y="40" dy=".35em" text-anchor="middle">Q</text><circle class="n" cx="384" cy="212" r="18"/><text class="t" x="384" y="212" dy=".35em" text-anchor="middle">Qb</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">R-S flip-flop from two cross-coupled NOR gates N1, N2; Q and Qb (Q bar) are the outputs.</figcaption></figure>

Answer frame. Open with the definition; draw the NOR-gate circuit with the feedback; give the truth table; explain the four states, stressing the invalid one; close with the memory role.

Pitfall: Write S=R=1 as invalid or forbidden, not as a valid state.

Asked: [14 marks] (Nov 2022, Jun 2023, Jun 2025) Write short notes on R-S flip-flop (options with J-K flip-flop, De Morgan's theorem, star-delta transformation, torque-slip characteristics, logic gates, electric and magnetic circuit, B-H curve)

J-K flip flop

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Definition. ==A J-K flip-flop is a clocked R-S flip-flop with feedback from the outputs to the inputs, which removes the invalid state by making J=K=1 toggle the output.==

Key points.

  1. It has inputs J (set) and K (reset), a clock input, and outputs $Q$ and $\bar Q$; $Q$ feeds back to the gate of K and $\bar Q$ to the gate of J.
  2. J=0, K=0 gives no change; J=0, K=1 resets ($Q=0$); J=1, K=0 sets ($Q=1$).
  3. J=1, K=1 toggles the output, $Q_{n+1}=\bar Q_n$, so the invalid condition of the R-S flip-flop does not occur.
  4. Characteristic equation: $Q_{n+1}=J\bar Q_n+\bar K Q_n$.
  5. Race-around: if the clock pulse stays high longer than the propagation delay while J=K=1, the output toggles repeatedly and the final state is uncertain.
  6. It is cured by a master-slave arrangement or edge triggering, so the output changes only once per clock.

Truth table.

J K $Q_{n+1}$ State
0 0 $Q_n$ No change
0 1 0 Reset
1 0 1 Set
1 1 $\bar Q_n$ Toggle

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u5-03" viewBox="0 0 510 252" width="510" height="252" role="img" aria-label="J-K flip-flop: two 3-input NAND gates G1, G2 drive an R-S latch FF; Q and Qb feed back."><style>#dsfig-u5-03 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u5-03 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u5-03 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u5-03 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u5-03 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u5-03 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u5-03 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u5-03 .t{fill:#16181D;font-weight:500}#dsfig-u5-03 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u5-03 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u5-03 .dot{fill:#16181D}#dsfig-u5-03 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u5-03 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u5-03 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u5-03 .ah{fill:#454C5A}#dsfig-u5-03 .ah.hi{fill:#2340B8}#dsfig-u5-03 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u5-03 .wl .t{font-size:12px;font-weight:700}#dsfig-u5-03 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u5-03 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u5-03 .e{stroke:#B1B7C3}html.dark #dsfig-u5-03 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u5-03 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u5-03 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u5-03 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u5-03 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u5-03 .t{fill:#E6E8ED}html.dark #dsfig-u5-03 .t.inv{fill:#0F1115}html.dark #dsfig-u5-03 .kd{stroke:#E6E8ED}html.dark #dsfig-u5-03 .dot{fill:#E6E8ED}html.dark #dsfig-u5-03 .ann{fill:#8FA3FF}html.dark #dsfig-u5-03 .lbl{fill:#858D9C}html.dark #dsfig-u5-03 .ptr{fill:#8FA3FF}html.dark #dsfig-u5-03 .ah{fill:#B1B7C3}html.dark #dsfig-u5-03 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u5-03 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u5-03 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u5-03 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah15" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh15" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L165.2,40" marker-end="url(#ah15)"/><path class="e" d="M59,212 L165.2,212" marker-end="url(#ah15)"/><path class="e" d="M59,126 L311.4,126" marker-end="url(#ah15)"/><path class="e" d="M202.6,49.6 L314.3,115.4" marker-end="url(#ah15)"/><path class="e" d="M202.6,202.4 L314.3,136.6" marker-end="url(#ah15)"/><path class="e" d="M348.5,115.9 L452.2,51.1" marker-end="url(#ah15)"/><path class="e" d="M348.5,136.1 L452.2,200.9" marker-end="url(#ah15)"/><path class="e" d="M453.8,202.2 L204.2,50.9" marker-end="url(#ah15)"/><path class="e" d="M453.8,49.8 L204.2,201.1" marker-end="url(#ah15)"/><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">J</text><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">Clk</text><circle class="n" cx="40" cy="212" r="18"/><text class="t" x="40" y="212" dy=".35em" text-anchor="middle">K</text><circle class="n" cx="186.2" cy="40" r="18"/><text class="t" x="186.2" y="40" dy=".35em" text-anchor="middle">G1</text><circle class="n" cx="186.2" cy="212" r="18"/><text class="t" x="186.2" y="212" dy=".35em" text-anchor="middle">G2</text><circle class="n" cx="332.4" cy="126" r="18"/><text class="t" x="332.4" y="126" dy=".35em" text-anchor="middle">FF</text><circle class="n" cx="470" cy="40" r="18"/><text class="t" x="470" y="40" dy=".35em" text-anchor="middle">Q</text><circle class="n" cx="470" cy="212" r="18"/><text class="t" x="470" y="212" dy=".35em" text-anchor="middle">Qb</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">J-K flip-flop: two 3-input NAND gates G1, G2 drive an R-S latch FF; Q and Qb feed back.</figcaption></figure>

Answer frame. Open with the definition; draw the symbol or the gated circuit with feedback; give the truth table; explain toggling, then race-around and its cure; close with the master-slave remedy.

Asked: [14 marks] (Dec 2023, Nov 2022, Jun 2023) Write a short note on J-K flip flop (options with dependent and independent sources, open and short circuit test, De Morgan's theorem)

Introduction to Semiconductors

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Not asked since 2022</span>

Definition. <mark>A semiconductor is a material whose conductivity lies between a conductor and an insulator, such as silicon and germanium, and rises with temperature and doping.</mark>

Key points.

  1. Intrinsic semiconductors are pure crystals in which thermal energy creates equal numbers of free electrons and holes.
  2. Extrinsic semiconductors are doped: n-type uses pentavalent donors (P, As) with electrons as majority carriers; p-type uses trivalent acceptors (B, Ga) with holes as majority carriers.
  3. Silicon has band gap about 1.1 eV and germanium about 0.7 eV.
  4. Unlike metals, a semiconductor has a negative temperature coefficient of resistance.

Diodes

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Not asked since 2022</span>

Definition. <mark>A diode is a two-terminal device formed by a p-n junction that conducts current easily in the forward direction and blocks it in the reverse direction.</mark>

Key points.

  1. Joining p and n type material creates a depletion region with a barrier potential of about 0.7 V (Si) and 0.3 V (Ge).
  2. Forward bias (anode positive) narrows the depletion region, so the diode conducts once the barrier is overcome.
  3. Reverse bias widens the depletion region and only a tiny leakage current flows.
  4. Its main use is rectification, converting AC to DC; the Zener diode is used for voltage regulation in breakdown.

V-I characteristics

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Medium weight</span>

Definition. <mark>The V-I characteristic of a p-n junction diode is the graph of diode current against applied voltage, with a forward region and a reverse region.</mark>

Key points.

  1. Forward bias: up to the cut-in (knee) voltage, 0.7 V for Si and 0.3 V for Ge, the current is negligible because the applied voltage has not overcome the barrier potential.
  2. Beyond the knee the current rises exponentially in mA, $I=I_0(e^{V/\eta V_T}-1)$, and the diode acts almost as a closed switch.
  3. Reverse bias: only a small reverse saturation current $I_0$ (in $\mu$A for Ge, nA for Si) flows, due to minority carriers, and it is nearly constant with voltage.
  4. At the reverse breakdown voltage $V_{BR}$ the current rises sharply by Zener or avalanche breakdown, and the diode can be damaged unless the current is limited.
  5. Axes: forward current $I_F$ in mA and voltage $V_F$ in the first quadrant; reverse voltage $V_R$ and current $I_R$ in $\mu$A in the third quadrant.

Diagram. <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u5-04" viewBox="0 0 510 295" width="510" height="295" role="img" aria-label="Diode V-I curve, origin O: reverse breakdown VBR, saturation current Io, knee Vg (0.7 V Si, 0.3 V Ge), forward rise"><style>#dsfig-u5-04 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u5-04 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u5-04 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u5-04 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u5-04 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u5-04 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u5-04 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u5-04 .t{fill:#16181D;font-weight:500}#dsfig-u5-04 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u5-04 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u5-04 .dot{fill:#16181D}#dsfig-u5-04 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u5-04 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u5-04 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u5-04 .ah{fill:#454C5A}#dsfig-u5-04 .ah.hi{fill:#2340B8}#dsfig-u5-04 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u5-04 .wl .t{font-size:12px;font-weight:700}#dsfig-u5-04 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u5-04 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u5-04 .e{stroke:#B1B7C3}html.dark #dsfig-u5-04 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u5-04 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u5-04 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u5-04 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u5-04 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u5-04 .t{fill:#E6E8ED}html.dark #dsfig-u5-04 .t.inv{fill:#0F1115}html.dark #dsfig-u5-04 .kd{stroke:#E6E8ED}html.dark #dsfig-u5-04 .dot{fill:#E6E8ED}html.dark #dsfig-u5-04 .ann{fill:#8FA3FF}html.dark #dsfig-u5-04 .lbl{fill:#858D9C}html.dark #dsfig-u5-04 .ptr{fill:#8FA3FF}html.dark #dsfig-u5-04 .ah{fill:#B1B7C3}html.dark #dsfig-u5-04 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u5-04 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u5-04 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u5-04 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah16" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh16" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M58.4,250.1 L150.6,225.5"/><path class="e" d="M187.9,218.7 L236.1,213.9"/><path class="e" d="M274,212 L322,212"/><path class="e hi" d="M352.4,196.8 L458.6,55.2"/><g class="wl"><rect x="66.6" y="228.8" width="75.9" height="18" rx="9"/><text class="t" x="104.5" y="237.8" dy=".35em" text-anchor="middle">breakdown</text></g><g class="wl"><rect x="198.8" y="207.3" width="26.4" height="18" rx="9"/><text class="t" x="212" y="216.3" dy=".35em" text-anchor="middle">Io</text></g><g class="wl"><rect x="256.9" y="203" width="82.2" height="18" rx="9"/><text class="t" x="298" y="212" dy=".35em" text-anchor="middle">below-knee</text></g><g class="wl hi"><rect x="360.8" y="117" width="89.4" height="18" rx="9"/><text class="t" x="405.5" y="126" dy=".35em" text-anchor="middle">exponential</text></g><circle class="n" cx="40" cy="255" r="18"/><text class="t" x="40" y="255" dy=".35em" text-anchor="middle">VBR</text><circle class="n" cx="169" cy="220.6" r="18"/><text class="t" x="169" y="220.6" dy=".35em" text-anchor="middle">Io</text><circle class="n" cx="255" cy="212" r="18"/><text class="t" x="255" y="212" dy=".35em" text-anchor="middle">O</text><circle class="n" cx="341" cy="212" r="18"/><text class="t" x="341" y="212" dy=".35em" text-anchor="middle">Vg</text><circle class="n" cx="470" cy="40" r="18"/><text class="t" x="470" y="40" dy=".35em" text-anchor="middle">F</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">Diode V-I curve, origin O: reverse breakdown VBR, saturation current Io, knee Vg (0.7 V Si, 0.3 V Ge), forward rise</figcaption></figure>

Answer frame. Open with the definition; draw the two-quadrant curve with the knee, $I_0$ and $V_{BR}$ labelled (mA scale forward, $\mu$A reverse); explain forward, reverse and breakdown in that order; close with the Si/Ge knee values.

Pitfall: Use different scales for the two quadrants, mA forward and $\mu$A reverse, and label them.

Asked: [7 marks] (Jun 2023, Jun 2025) Draw and explain the V-I characteristics of a PN junction / diode.

Bipolar junction transistors (BJT) and their working

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Low weight</span>

Definition. <mark>A bipolar junction transistor is a three-terminal, current-controlled device with two p-n junctions, in which a small base current controls a large collector current.</mark>

Key points.

  1. It is npn or pnp, with three regions: emitter (heavily doped), base (thin, lightly doped) and collector (moderately doped, largest area).
  2. For amplification the emitter-base junction is forward biased and the collector-base junction reverse biased.
  3. In an npn transistor the emitter injects electrons into the thin base; only about 1% recombine to form the base current, and the rest are swept across to the collector.
  4. Currents: $I_E=I_B+I_C$, with $I_C=\beta I_B$, $\alpha=I_C/I_E$ and $\beta=\alpha/(1-\alpha)$.
  5. Its characteristics are drawn in the CE configuration: input $I_B$ vs $V_{BE}$ (like a forward diode) and output $I_C$ vs $V_{CE}$ (see the CE section below).

Asked: [7 marks] (Jun 2022) Explain principle of operation and characteristics of BJT.

Introduction to CC, CB & CE transistor configurations

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">High weight</span>

Definition. <mark>A transistor configuration is named after the terminal common to input and output: common base (CB), common emitter (CE) or common collector (CC).</mark>

Key points.

  1. CE input characteristic is $I_B$ against $V_{BE}$ at constant $V_{CE}$; it resembles a forward diode curve with knee near 0.7 V (Si).
  2. CE output characteristic is $I_C$ against $V_{CE}$ for fixed values of $I_B$; each curve rises steeply, then flattens.
  3. Active region: emitter junction forward and collector junction reverse biased; $I_C\approx\beta I_B$, the transistor works as a linear amplifier.
  4. Saturation region ($V_{CE}<V_{CE(sat)}\approx0.2$ V, the knee): both junctions forward biased, $I_C$ is maximum, and the transistor acts as a closed switch.
  5. Cutoff region ($I_B=0$): both junctions reverse biased, only the small leakage $I_{CEO}$ flows, and the transistor acts as an open switch.
  6. CB: input characteristic is $V_{EB}$ against $I_E$ at constant $V_{CB}$; it is a forward diode curve. Output is $I_C$ against $V_{CB}$ at constant $I_E$: nearly flat lines in the active region, with $I_C\approx I_E$.
  7. In CB, $\alpha=\Delta I_C/\Delta I_E$ (at constant $V_{CB}$), about 0.95-0.99, so there is no current gain, but the voltage gain is high.
  8. CB output regions: active ($V_{CB}$ reverse, $I_C\approx\alpha I_E$), saturation (small forward $V_{CB}$, $I_C$ falls rapidly), cutoff ($I_E=0$, $I_C=I_{CBO}$).

Diagram (CE test circuit). <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u5-05" viewBox="0 0 527.2 166" width="527.2" height="166" role="img" aria-label="NPN CE circuit: base supply VBB with RB (base input), collector supply VCC with RC; emitter common to both; ammeters read IB, IC."><style>#dsfig-u5-05 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u5-05 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u5-05 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u5-05 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u5-05 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u5-05 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u5-05 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u5-05 .t{fill:#16181D;font-weight:500}#dsfig-u5-05 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u5-05 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u5-05 .dot{fill:#16181D}#dsfig-u5-05 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u5-05 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u5-05 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u5-05 .ah{fill:#454C5A}#dsfig-u5-05 .ah.hi{fill:#2340B8}#dsfig-u5-05 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u5-05 .wl .t{font-size:12px;font-weight:700}#dsfig-u5-05 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u5-05 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u5-05 .e{stroke:#B1B7C3}html.dark #dsfig-u5-05 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u5-05 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u5-05 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u5-05 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u5-05 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u5-05 .t{fill:#E6E8ED}html.dark #dsfig-u5-05 .t.inv{fill:#0F1115}html.dark #dsfig-u5-05 .kd{stroke:#E6E8ED}html.dark #dsfig-u5-05 .dot{fill:#E6E8ED}html.dark #dsfig-u5-05 .ann{fill:#8FA3FF}html.dark #dsfig-u5-05 .lbl{fill:#858D9C}html.dark #dsfig-u5-05 .ptr{fill:#8FA3FF}html.dark #dsfig-u5-05 .ah{fill:#B1B7C3}html.dark #dsfig-u5-05 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u5-05 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u5-05 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u5-05 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah17" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh17" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,126 L130.8,126" marker-end="url(#ah17)"/><path class="e" d="M170.8,126 L242.6,126" marker-end="url(#ah17)"/><path class="e" d="M472.1,114.4 L392,52.8" marker-end="url(#ah17)"/><path class="e" d="M360.3,51.6 L280.2,113.2" marker-end="url(#ah17)"/><g class="wl"><rect x="194.5" y="117" width="26.4" height="18" rx="9"/><text class="t" x="207.7" y="126" dy=".35em" text-anchor="middle">IB</text></g><g class="wl"><rect x="306.3" y="74" width="26.4" height="18" rx="9"/><text class="t" x="319.5" y="83" dy=".35em" text-anchor="middle">IC</text></g><circle class="n" cx="40" cy="126" r="18"/><text class="t" x="40" y="126" dy=".35em" text-anchor="middle">VBB</text><circle class="n" cx="151.8" cy="126" r="18"/><text class="t" x="151.8" y="126" dy=".35em" text-anchor="middle">RB</text><circle class="n" cx="263.6" cy="126" r="18"/><text class="t" x="263.6" y="126" dy=".35em" text-anchor="middle">T</text><circle class="n" cx="375.4" cy="40" r="18"/><text class="t" x="375.4" y="40" dy=".35em" text-anchor="middle">RC</text><circle class="n" cx="487.2" cy="126" r="18"/><text class="t" x="487.2" y="126" dy=".35em" text-anchor="middle">VCC</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">NPN CE circuit: base supply VBB with RB (base input), collector supply VCC with RC; emitter common to both; ammeters read IB, IC.</figcaption></figure>

Diagram (CB test circuit). <figure class="ds-fig" style="margin:1.4rem 0;overflow-x:auto"><svg xmlns="http://www.w3.org/2000/svg" id="dsfig-u5-06" viewBox="0 0 527.2 80" width="527.2" height="80" role="img" aria-label="NPN CB circuit: base common to both loops; VEE forward biases emitter-base, VCC reverse biases collector-base."><style>#dsfig-u5-06 .e{stroke:#454C5A;stroke-width:1.4;fill:none}#dsfig-u5-06 .e.hi{stroke:#2340B8;stroke-width:2.6}#dsfig-u5-06 .n{fill:#FFFFFF;stroke:#16181D;stroke-width:1.4}#dsfig-u5-06 .n.hi{fill:#E3E9FC;stroke:#2340B8;stroke-width:2.2}#dsfig-u5-06 .n.rb-b{fill:#16181D;stroke:#16181D}#dsfig-u5-06 .n.rb-r{fill:#BD3227;stroke:#BD3227}#dsfig-u5-06 text{font-family:"JetBrains Mono",ui-monospace,Menlo,Consolas,monospace;font-size:13px}#dsfig-u5-06 .t{fill:#16181D;font-weight:500}#dsfig-u5-06 .t.inv{fill:#FFFFFF;font-weight:700}#dsfig-u5-06 .kd{stroke:#16181D;stroke-width:1.2}#dsfig-u5-06 .dot{fill:#16181D}#dsfig-u5-06 .ann{fill:#2340B8;font-size:11px;font-weight:700}#dsfig-u5-06 .lbl{fill:#6F7787;font-family:system-ui,-apple-system,sans-serif;font-size:12px;font-weight:700}#dsfig-u5-06 .ptr{fill:#2340B8;font-size:12px;font-weight:700}#dsfig-u5-06 .ah{fill:#454C5A}#dsfig-u5-06 .ah.hi{fill:#2340B8}#dsfig-u5-06 .wl rect{fill:#FFFFFF;stroke:#DCE0E7}#dsfig-u5-06 .wl .t{font-size:12px;font-weight:700}#dsfig-u5-06 .wl.hi rect{fill:#2340B8;stroke:#2340B8}#dsfig-u5-06 .wl.hi .t{fill:#FFFFFF}html.dark #dsfig-u5-06 .e{stroke:#B1B7C3}html.dark #dsfig-u5-06 .e.hi{stroke:#8FA3FF}html.dark #dsfig-u5-06 .n{fill:#161920;stroke:#E6E8ED}html.dark #dsfig-u5-06 .n.hi{fill:#1E2748;stroke:#8FA3FF}html.dark #dsfig-u5-06 .n.rb-b{fill:#E6E8ED;stroke:#E6E8ED}html.dark #dsfig-u5-06 .n.rb-r{fill:#FF7E71;stroke:#FF7E71}html.dark #dsfig-u5-06 .t{fill:#E6E8ED}html.dark #dsfig-u5-06 .t.inv{fill:#0F1115}html.dark #dsfig-u5-06 .kd{stroke:#E6E8ED}html.dark #dsfig-u5-06 .dot{fill:#E6E8ED}html.dark #dsfig-u5-06 .ann{fill:#8FA3FF}html.dark #dsfig-u5-06 .lbl{fill:#858D9C}html.dark #dsfig-u5-06 .ptr{fill:#8FA3FF}html.dark #dsfig-u5-06 .ah{fill:#B1B7C3}html.dark #dsfig-u5-06 .ah.hi{fill:#8FA3FF}html.dark #dsfig-u5-06 .wl rect{fill:#161920;stroke:#2A2E37}html.dark #dsfig-u5-06 .wl.hi rect{fill:#8FA3FF;stroke:#8FA3FF}html.dark #dsfig-u5-06 .wl.hi .t{fill:#0F1115}</style><defs><marker id="ah18" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah" d="M0,1 L9,5 L0,9 z"/></marker><marker id="ahh18" viewBox="0 0 10 10" refX="9" refY="5" markerWidth="7" markerHeight="7" orient="auto-start-reverse"><path class="ah hi" d="M0,1 L9,5 L0,9 z"/></marker></defs><path class="e" d="M59,40 L130.8,40" marker-end="url(#ah18)"/><path class="e" d="M170.8,40 L242.6,40" marker-end="url(#ah18)"/><path class="e" d="M282.6,40 L354.4,40" marker-end="url(#ah18)"/><path class="e" d="M394.4,40 L466.2,40" marker-end="url(#ah18)"/><g class="wl"><rect x="194.5" y="31" width="26.4" height="18" rx="9"/><text class="t" x="207.7" y="40" dy=".35em" text-anchor="middle">IE</text></g><g class="wl"><rect x="306.3" y="31" width="26.4" height="18" rx="9"/><text class="t" x="319.5" y="40" dy=".35em" text-anchor="middle">IC</text></g><circle class="n" cx="40" cy="40" r="18"/><text class="t" x="40" y="40" dy=".35em" text-anchor="middle">VEE</text><circle class="n" cx="151.8" cy="40" r="18"/><text class="t" x="151.8" y="40" dy=".35em" text-anchor="middle">RE</text><circle class="n" cx="263.6" cy="40" r="18"/><text class="t" x="263.6" y="40" dy=".35em" text-anchor="middle">T</text><circle class="n" cx="375.4" cy="40" r="18"/><text class="t" x="375.4" y="40" dy=".35em" text-anchor="middle">RC</text><circle class="n" cx="487.2" cy="40" r="18"/><text class="t" x="487.2" y="40" dy=".35em" text-anchor="middle">VCC</text></svg><figcaption style="font-size:.82em;opacity:.72;margin-top:.45rem">NPN CB circuit: base common to both loops; VEE forward biases emitter-base, VCC reverse biases collector-base.</figcaption></figure>

Comparison.

Property CB CE CC
Common terminal Base Emitter Collector
Input, output Emitter, collector Base, collector Base, emitter
Current gain $\alpha<1$ $\beta$ (high, 20-500) $\gamma=\beta+1$
Voltage gain High High Less than 1
Input resistance Low Medium Very high
Phase shift 0 degrees 180 degrees 0 degrees
Use High-frequency amplifier General amplifier Buffer (emitter follower)

Answer frame.

  • CE output: open by defining CE and the active region; draw the circuit, then the $I_C$-$V_{CE}$ family for rising $I_B$ with the three regions marked; explain active, saturation, cutoff; if asked for both characteristics, add the input curve first; close by saying active is used for amplifiers and saturation/cutoff for switching.
  • CB: open with the definition of CB; draw the CB circuit and both curves; give the biasing, then input, output regions and $\alpha$; close with $\alpha<1$ and $I_E=I_B+I_C$.

Asked: [7 marks] (Nov 2022, Dec 2024) Draw and explain the output characteristic of a NPN transistor operation in CE configuration / with input and output characteristics explain the operation of BJT in common emitter configuration.

Asked: [7 marks] (Jun 2023, Jun 2025) Draw the circuit and explain the characteristics of CB configuration / explain the working principle of common base transistor.

Different configurations and modes of operation of BJT

<span style="display:inline-block;padding:.16em .6em;border:1.5px solid currentColor;border-radius:999px;font-size:.68em;font-weight:700;letter-spacing:.06em;text-transform:uppercase;opacity:.75">Low weight</span>

Definition. <mark>A BJT works in cutoff, active or saturation mode, set by its bias, and its operating (Q) point is the dc $I_C$ and $V_{CE}$ at zero signal.</mark>

Key points.

  1. Cutoff: both junctions reverse biased, $I_C\approx0$ (switch OFF).
  2. Active: emitter junction forward and collector junction reverse biased (amplifier).
  3. Saturation: both junctions forward biased, $V_{CE}\approx0.2$ V (switch ON).
  4. Fixed bias: $I_B=\dfrac{V_{CC}-V_{BE}}{R_B}$, $I_C=\beta I_B$, $V_{CE}=V_{CC}-I_CR_C$.

Example (Dec 2023). Given $V_{CC}=24$ V, $R_B=220$ k$\Omega$, $R_C=4.7$ k$\Omega$; assume Si, $V_{BE}=0.7$ V, $\beta=100$.

Step Working
$I_B$ $(24-0.7)/220\text{k}=105.9\ \mu$A
$I_C=\beta I_B$ $100\times105.9\ \mu\text{A}=10.59$ mA
$V_{CE}$ $24-10.59\text{m}\times4.7\text{k}=-25.8$ V, impossible
Check $I_{C(sat)}=24/4.7\text{k}=5.1$ mA is less than 10.59 mA

The transistor is driven into saturation, so $I_C$ is limited to 5.1 mA and $V_{CE}\approx0.2$ V. Q-point: $I_B=105.9\ \mu$A, $I_C\approx5.1$ mA, $V_{CE}\approx0.2$ V (saturation). If the examiner's expected active-region formula is used, write $Q(V_{CE},I_C)$ in terms of $\beta$ ($I_C=\beta\times105.9\ \mu$A) and state the saturation check.

Asked: [7 marks] (Dec 2023) In a fixed bias circuit using n-p-n transistor, find the operating point if $V_{CC}=24$ V, $R_B=220$ k, $R_C=4.7$ k.

Last-minute revision

  • Binary to octal groups 3 bits; binary to hex groups 4 bits; $(257)_8=(10101111)_2$; $(21.625)_{10}=(25.5)_8$; $(BC.2)_{16}=(274.1)_8$; $(33)_{10}=(201)_4$.
  • De Morgan: $\overline{A+B}=\bar A\bar B$ and $\overline{AB}=\bar A+\bar B$.
  • NAND and NOR are universal gates; XOR output is 1 when inputs differ.
  • Full adder: $Sum=A\oplus B\oplus C_{in}$, $C_{out}=AB+C_{in}(A\oplus B)$; two half adders plus OR.
  • R-S flip-flop: S=R=1 is invalid; S=R=0 holds; S=1 sets; R=1 resets.
  • J-K flip-flop: J=K=1 toggles; race-around cured by master-slave or edge triggering.
  • Diode knee: 0.7 V Si, 0.3 V Ge; reverse current $I_0$ in $\mu$A; breakdown at $V_{BR}$.
  • BJT: $I_E=I_B+I_C$, $\alpha=I_C/I_E$, $\beta=I_C/I_B$, $\beta=\alpha/(1-\alpha)$.
  • CE regions: active (amplifier), saturation (ON), cutoff ($I_B=0$, OFF).
  • Fixed bias: $I_B=(V_{CC}-V_{BE})/R_B$, $V_{CE}=V_{CC}-I_CR_C$; check saturation with $V_{CC}/R_C$.

Memory hooks

  • NAND and NOR are "Not-And, Not-Or" and can build everything: universal.
  • De Morgan: break the bar, change the sign.
  • J-K: J=K=1 "Jumps" to the opposite state (toggle).
  • BJT amplifier bias: Emitter Forward, Collector Reverse.
  • CE = 180 degrees phase shift, CC = emitter follower, CB = smallest input resistance.

Coverage checklist

  • Number systems & Their conversion used in digital electronics: Dec 2024 conversions.
  • De morgan's theorem: covered in the short notes of Nov 2022, Jun 2023, Dec 2023.
  • Logic Gates: Jun 2025 short note.
  • half and full adder circuits: Dec 2023 full adder.
  • R-S flip flop: Nov 2022, Jun 2023, Jun 2025 short notes.
  • J-K flip flop: Dec 2023 short note (and Nov 2022 option).
  • Introduction to Semiconductors: definition and key points.
  • Diodes: definition and key points.
  • V-I characteristics: Jun 2023, Jun 2025.
  • Bipolar junction transistors (BJT) and their working: Jun 2022.
  • introduction to CC, CB & CE transistor configurations: Nov 2022, Dec 2024, Jun 2023, Jun 2025.
  • different configurations and modes of operation of BJT: Dec 2023 operating point.
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