VLSI circuits and systems (EX-803 (C)) - Unit 4 Short Notes

UNIT 4: Advanced Digital VLSI Design

I. MOS Transistor Fundamentals

A. Electrical Properties and Characteristics

• MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is the fundamental building block.

• Key Regions of Operation:

  • Cutoff: $$\displaystyle V_{GS} < V_{th} $$, no channel, $$\displaystyle I_D \approx 0 $$.

  • Triode/Linear: $$\displaystyle V_{GS} > V_{th} $$ and $$\displaystyle V_{DS} < V_{GS} - V_{th} $$, channel exists, $$\displaystyle I_D $$ depends on $$\displaystyle V_{GS} $$ and $$\displaystyle V_{DS} $$.

  • Saturation: $$\displaystyle V_{GS} > V_{th} $$ and $$\displaystyle V_{DS} \geq V_{GS} - V_{th} $$, channel pinched off near drain, $$\displaystyle I_D $$ primarily depends on $$\displaystyle V_{GS} $$.

• Current-Voltage Relationships (for long-channel, ideal model):

  • Triode: $$\displaystyle I_D = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2} \right] $$

  • Saturation: $$\displaystyle I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{th})^2 (1 + \lambda V_{DS}) $$

  [!TIP] Exam Focus: The saturation current equation includes the channel length modulation term $$\displaystyle (1 + \lambda V_{DS}) $$. This is a key non-ideal effect.

B. Threshold Voltage, Mobility, and Channel Length Modulation

• Threshold Voltage ($$\displaystyle V_{th} $$): Minimum $$\displaystyle V_{GS} $$ to create a conductive channel. Affected by body bias ($$\displaystyle V_{SB} $$), oxide thickness, and doping.

$$V_{th} = V_{FB} + 2\phi_F + \frac{\sqrt{2\epsilon_{si} q N_A (2\phi_F + V_{SB})}}{C_{ox}}$$

• Mobility ($$\displaystyle \mu_n $$, $$\displaystyle \mu_p $$): Carrier drift velocity per unit electric field. $$\displaystyle \mu_n > \mu_p $$ (typically 2-3x). Decreases with high vertical field (surface scattering).

• Channel Length Modulation (λ): Finite output conductance in saturation due to channel length reduction as $$\displaystyle V_{DS} $$ increases. Analogous to Early effect in BJTs.

C. Subthreshold Conduction and Leakage Currents

• Subthreshold Region: $$\displaystyle V_{GS} < V_{th} $$ but > ~0. Current flows exponentially.

$$I_D \approx I_0 e^{\frac{V_{GS} - V_{th}}{nV_T}} \left(1 - e^{\frac{-V_{DS}}{V_T}}\right)$$

where $$\displaystyle V_T = kT/q \approx 26\,mV $$ at room temp, $n$ is subthreshold slope factor (1-1.5).

• Leakage Components:

  1. Subthreshold Leakage: Dominant in low $$\displaystyle V_{th} $$ or high-temperature designs.

  2. Gate Oxide Tunneling: Current through thin gate oxide ($$\displaystyle I_{gate} \propto e^{-t_{ox}} $$).

  3. Junction Leakage: Reverse-biased source/drain to body junction.

  [!TIP] Common Pitfall: Subthreshold current is exponential in $$\displaystyle V_{GS} - V_{th} $$, not quadratic. This is critical for low-power design.

II. CMOS Inverter Design and Scaling

A. Need for Scaling in VLSI

• To increase integration density (more transistors/chip).

• To improve performance (higher speed, lower delay).

• To reduce cost per function and power consumption per transistor.

• To enable new applications (portable, high-performance computing).

B. Scaling Principles

C. Fundamental Units: Transistor Sizing, Noise Margins, DC Characteristics

• Transistor Sizing (β ratio): For symmetric rise/fall times, $$\displaystyle (W/L)_p = 2 \times (W/L)_n $$ in typical processes (due to $$\displaystyle \mu_p \approx \mu_n/2 $$).

• Noise Margins:

  • $$\displaystyle NM_L = V_{IL} - V_{OL} $$ (Low Noise Margin)

  • $$\displaystyle NM_H = V_{OH} - V_{IH} $$ (High Noise Margin)

  • Ideal CMOS Inverter: $$\displaystyle V_{IL} = V_{IH} = V_M = V_{OL} = V_{OH} = V_{DD}/2 $$ → $$\displaystyle NM_L = NM_H = V_{DD}/2 $$.

• DC Transfer Curve: Characteristic S-shaped curve. Voltage Transfer Point (VTP) is where $$\displaystyle V_{in} = V_{out} $$. For symmetric inverter, $$\displaystyle VTP = V_{DD}/2 $$.

III. Layout Design and Design Rules

A. Layout Design Rules

• Purpose: Ensure manufacturability and electrical connectivity.

• Lambda-based Rules (λ): All dimensions expressed as multiples of λ (half the minimum feature size). Simple, technology-independent.

  • Minimum Width (W): e.g., 2λ for poly, 3λ for metal1.

  • Minimum Spacing (S): e.g., 2λ between poly lines.

  • Extension/Overlap: e.g., active must extend 1λ beyond poly.

• Micron Rules: Absolute dimensions in microns (μm). More precise, technology-specific.

B. Stick Diagrams and their Role in Layout Planning

• Stick Diagram: Abstract representation using colored lines (sticks) for each layer (diffusion, poly, metal, etc.). No width or exact placement.

• Purpose:

  1. Plan floorplan and routing early.

  2. Visualize connectivity and layer assignments.

  3. Check for design rule violations conceptually.

  4. Bridge schematic and final layout.

C. Layout Diagram for NAND and NOR Gates

• General Principle: Use diffusion sharing to minimize area.

• 2-Input NAND:

  • Two NMOS in series share a common diffusion region.

  • Two PMOS in parallel have separate diffusions, connected to $$\displaystyle V_{DD} $$.

  • Poly runs cross both NMOS and PMOS diffusions.

  • Metal1 connects source/drain terminals to pins.

  • DiagramCANVAS: Standard CMOS NAND layout showing series NMOS, parallel PMOS, poly cross, metal1 contacts.

• 2-Input NOR:

  • Two NMOS in parallel share a common source diffusion to GND.

  • Two PMOS in series share a common diffusion.

  • DiagramCANVAS: Standard CMOS NOR layout showing parallel NMOS, series PMOS, poly cross.

  [!TIP] Exam Tip: Be able to sketch stick diagrams and final layouts for NAND/NOR. Remember: Series = shared diffusion, Parallel = separate diffusions.

IV. Combinational Logic Design

A. CMOS Implementation of Logic Gates (Static CMOS)

• Principle: Implement logic function as $F$ and $\overline{F}$ using complementary pull-up (PMOS) and pull-down (NMOS) networks.

• Pull-Down Network (PDN): NMOS transistors, implements $F$. Conducts when $$\displaystyle F=1 $$ → pulls output to GND.

• Pull-Up Network (PUN): PMOS transistors, implements $\overline{F}$. Conducts when $$\displaystyle F=0 $$ → pulls output to $$\displaystyle V_{DD} $$.

• Duality: PDN is dual of PUN (series ↔ parallel, N-type ↔ P-type).

• Example: $$\displaystyle F = A + B $$ (NOR2)

  • PDN (for $F$): Parallel NMOS (A and B).

  • PUN (for $$\displaystyle \overline{F} = \overline{A+B} $$): Series PMOS ($\overline{A}$ and $\overline{B}$).

B. Design and Verification using Truth Tables

1. Derive Boolean expression from truth table.

2. Implement PDN for $F$ (series for AND, parallel for OR).

3. Implement dual PUN for $\overline{F}$.

4. Verify: For each input combo, either PDN or PUN conducts, never both (no static power).

5. Check output polarity matches truth table.

C. Pass Transistor Logic (PTL) and its Applications

• Concept: Use transistors as switches to pass signals directly, not just as inverters.

• Basic Pass Transistor: NMOS passes a strong '0' but weak '1' ($$\displaystyle V_{DD} - V_{th} $$). PMOS passes strong '1' but weak '0'.

• Transmission Gate (TG): Parallel NMOS+PMOS controlled by complementary signals. Passes both '0' and '1' strongly.

  • Applications: Multiplexers, bus switches, latches, XOR gates.

  • Advantage: Fewer transistors than static CMOS for some functions (e.g., 2:1 MUX: 4 TGs vs 8 transistors in CMOS).

  • Disadvantage: Signal degradation (voltage drop) if only NMOS used; need level-restoration circuits.

  [!TIP] Key Difference: Static CMOS has full rail-to-rail swing, zero static power. PTL has reduced voltage swing, potential static power if not carefully designed.

V. Timing and Delay Analysis

A. Elmore's Constant and RC Delay Model

• RC Delay Model: Approximate circuit as an RC network. Delay $$\displaystyle \tau \approx 0.69 \times R_{eq} \times C_L $$.

  • $$\displaystyle R_{eq} $$: Equivalent resistance of the driving transistor (lookup table based on $W/L$).

  • $$\displaystyle C_L $$: Total load capacitance (gate caps + wire caps).

• Elmore's Constant ($$\displaystyle t_{pd} $$): More accurate for distributed RC trees.

$$t_{pd} = \sum_{i} R_i \cdot C_i$$

where sum is over all capacitors $$\displaystyle C_i $$, and $$\displaystyle R_i $$ is the resistance from the output node to the root along the path to $$\displaystyle C_i $$.

> [!TIP] **Calculation:** For a simple inverter driving a load $$\displaystyle C_L $$, $$\displaystyle t_{pd} = R_{eq,n} C_L $$ (for falling) or $$\displaystyle R_{eq,p} C_L $$ (for rising).

B. Propagation Delay Expression for CMOS Inverter

• Definition:

  • $$\displaystyle t_{pLH} $$: Low-to-High propagation delay (output rising).

  • $$\displaystyle t_{pHL} $$: High-to-Low propagation delay (output falling).

  • $$\displaystyle t_p = (t_{pLH} + t_{pHL})/2 $$ (average propagation delay).

• Expression (using RC model):

$$t_{pLH} \approx 0.69 \times R_p \times (C_{in,n} + C_{in,p} + C_{wire})$$

$$t_{pHL} \approx 0.69 \times R_n \times (C_{in,n} + C_{in,p} + C_{wire})$$

where $$\displaystyle C_{in,n}, C_{in,p} $$ are input gate capacitances of the next stage.

> [!BOX] **Final Formula:** For a chain of inverters, **delay scales with load capacitance and transistor resistance.** Sizing for equal delay: $$\displaystyle (W/L)_{n,i+1} = h \times (W/L)_{n,i} $$ where $h$ is the **logical effort** of the gate.

VI. Switch-Level Design: Transmission Gates

A. Structure and Operation of Transmission Gate

• Structure: Parallel combination of one NMOS and one PMOS transistor, with gates driven by complementary signals ($\overline{EN}$ for NMOS, $EN$ for PMOS).

• Operation:

  • When $$\displaystyle EN=1 $$: Both transistors ON → low-resistance bidirectional path.

  • When $$\displaystyle EN=0 $$: Both transistors OFF → high resistance (isolation).

• Advantage over single NMOS: Passes both logic '0' and '1' without threshold voltage drop ($$\displaystyle V_{DD} - V_{th} $$).

  [!TIP] Symbol: Standard symbol is a transmission gate with an inverted control input on the PMOS side.

B. Use in Multiplexers, Latches, and Analog Switches

• 2:1 Multiplexer: Two TGs controlled by select $S$ and $\overline{S}$. Selects between inputs $A$ and $B$.

• D-Latch (Transparent Latch): TG controlled by clock $CLK$ on data path, back-to-back inverters as storage. When $$\displaystyle CLK=1 $$, latch is transparent.

• Analog Switches: Used in sample-and-hold circuits, DACs due to low on-resistance and bidirectional capability.

VII. Sequential Circuit Design

A. Design Methodology for Latches and Flip-Flops

1. Identify State Element: Need to store 1 bit (latch) or edge-triggered bit (FF).

2. Choose Basic Cell: SR Latch (cross-coupled NOR/NAND), D Latch (TG + inverters).

3. Add Clocking: Use clocked TGs or gated inverters to create level-sensitive latch.

4. For Edge-Triggering: Use Master-Slave (two latches) or pulse-triggered techniques.

5. Ensure Hazard-Free: Avoid race-around condition in asynchronous SR latch.

6. Characterize Timing: Setup time ($$\displaystyle t_{su} $$), hold time ($$\displaystyle t_h $$), clock-to-Q delay ($$\displaystyle t_{cQ} $$).

B. Master-Slave Based Edge-Triggered Registers

• Structure: Two back-to-back latches (Master and Slave) clocked with opposite phases (e.g., Master on $CLK$, Slave on $\overline{CLK}$).

• Operation:

  • First half-cycle ($$\displaystyle CLK=1 $$): Master transparent, Slave opaque. Input $D$ propagates to Master output.

  • Second half-cycle ($$\displaystyle CLK=0 $$): Master opaque, Slave transparent. Master's stored value propagates to Slave output (final $Q$).

• Result: Output $Q$ changes only on falling edge of $CLK$ (negative edge-triggered). Positive edge-triggered uses inverted clocking.

• Advantage: Eliminates race-around condition (unstable oscillation in asynchronous SR latch when $$\displaystyle S=R=1 $$).

C. Timing Parameters

• Setup Time ($$\displaystyle t_{su} $$): Minimum time data ($D$) must be stable before the active clock edge.

• Hold Time ($$\displaystyle t_h $$): Minimum time data ($D$) must be stable after the active clock edge.

• Clock-to-Q Delay ($$\displaystyle t_{cQ} $$): Time from active clock edge to output ($Q$) becoming valid.

• Constraint: $$\displaystyle t_{clk} \geq t_{cQ} + t_{su} + t_{logic} + t_{setup(next)} $$ (for pipeline).

  [!BOX] Critical Path: The longest path through combinational logic between two flip-flops determines maximum clock frequency: $$\displaystyle f_{max} = 1 / (t_{cQ} + t_{pd,comb} + t_{su}) $$.

VIII. Clock Distribution Networks

A. Importance in Synchronous Design

• Provides a common timing reference to all sequential elements.

• Clock Skew (difference in clock arrival times) can reduce timing margin or cause failures.

• Clock Load is large (drives many FF gates), needs buffering.

• Clock Power can be a significant portion of total dynamic power.

B. Clock Distribution Techniques

1. Tree (H-Tree): Symmetric binary tree. Minimizes average skew, but load not balanced.

2. Grid (Mesh): Clock distributed via a grid of metal lines. Excellent skew control, but high capacitance and power.

3. Spine (with Buffers): Main spine with buffers driving local loads. Common in standard-cell designs.

4. Clock Gating: Insert logic (AND with enable) to stop clock to idle blocks, saving power.

C. Clock Skew and Its Minimization

• Skew ($$\displaystyle \phi_{skew} $$): $$\displaystyle \phi_{skew} = t_{ck}(FF_i) - t_{ck}(FF_j) $$.

• Negative Skew (useful skew): Deliberately skew clock to relax setup constraint for downstream FF (but tightens hold).

• Minimization Techniques:

  • Buffer Insertion: Insert identical buffers on long wires.

  • Load Balancing: Match capacitive loads at tree branches.

  • Use Low-Skew Buffers/Clock Trees: Dedicated library cells.

  • Placement: Place clock source centrally, use symmetric routing.

  [!TIP] Trade-off: Zero skew is ideal for max frequency, but small, controlled negative skew can improve yield by relaxing setup.

IX. Arithmetic Circuits

A. Adders

1. Ripple Carry Adder (RCA)

• Structure: Chain of 1-bit Full Adders (FA). Carry ripples from LSB to MSB.

• Delay: $$\displaystyle t_{pd} \approx N \times t_{carry} + t_{sum} $$. $O(N)$ delay.

• Area: Small, simple.

• Use: Small bit-widths (4-8 bits), where speed not critical.

2. Carry Look-Ahead Adder (CLA)

• Principle: Generate carry signals in parallel using generate ($$\displaystyle G_i $$) and propagate ($$\displaystyle P_i $$) signals.

  • $$\displaystyle G_i = A_i \cdot B_i $$ (Generate carry)

  • $$\displaystyle P_i = A_i \oplus B_i $$ (Propagate carry)

  • $$\displaystyle C_{i+1} = G_i + P_i C_i $$

• Look-Ahead Equations (4-bit example):

$$ \begin{aligned} C_1 &= G_0 + P_0 C_0 \\ C_2 &= G_1 + P_1 G_0 + P_1 P_0 C_0 \\ C_3 &= G_2 + P_2 G_1 + P_2 P_1 G_0 + P_2 P_1 P_0 C_0 \\ C_4 &= G_3 + P_3 G_2 + P_3 P_2 G_1 + P_3 P_2 P_1 G_0 + P_3 P_2 P_1 P_0 C_0 \end{aligned} $$

• Delay: $O(\log N)$ for carry generation (using 2-level logic). Sum generation adds one more gate delay.

• Area: Larger than RCA due to complex carry logic.

• Diagram:

  DiagramCANVAS: 4-bit CLA block diagram showing PG generation, carry look-ahead logic (CLU), and sum generation.

3. Carry Bypass Adder (CBA) - 16-bit Example

• Principle: For each block (e.g., 4-bit), compute block generate ($$\displaystyle G_{block} $$) and block propagate ($$\displaystyle P_{block} $$).

  • $$\displaystyle G_{block} = G_3 + P_3 G_2 + P_3 P_2 G_1 + P_3 P_2 P_1 G_0 $$

  • $$\displaystyle P_{block} = P_3 P_2 P_1 P_0 $$

• Operation:

  • If $$\displaystyle P_{block}=1 $$ and $$\displaystyle C_{in}=1 $$, then $$\displaystyle C_{out}=1 $$ (bypassed).

  • If $$\displaystyle G_{block}=1 $$, then $$\displaystyle C_{out}=1 $$ (generated).

  • Else, $$\displaystyle C_{out}=C_{in} $$ (ripple within block).

• 16-bit CBA: Divide into four 4-bit blocks. Use one CLA-like unit to compute block carries in parallel. Within each block, use RCA.

• Delay: $$\displaystyle t_{pd} \approx t_{PG} + t_{block-carry} + t_{ripple-in-block} $$. Faster than RCA, simpler than full CLA.

• Features: Good speed-area trade-off for medium N (8-32 bits).

B. Multipliers

1. Booth Multiplication Algorithm

• Purpose: Reduce number of partial products by encoding 3 bits at a time (with overlap).

• Booth Encoding (Radix-2): Examine $$\displaystyle x_i $$ and $$\displaystyle x_{i-1} $$ (LSB first).

  | $$\displaystyle x_i $$ | $$\displaystyle x_{i-1} $$ | Operation | Partial Product | | :--- | :--- | :--- | :--- | | 0 | 0 | +0 | 0...0 | | 0 | 1 | +Y | Y | | 1 | 0 | -Y | -Y (2's complement) | | 1 | 1 | 0 | 0...0 |

• Steps:

  1. Append $$\displaystyle x_{-1}=0 $$ to multiplicand $X$.

  2. For $$\displaystyle i=0 $$ to $n-1$: Based on $$\displaystyle (x_i, x_{i-1}) $$, select {0, +Y, -Y, 0}.

  3. Arithmetic right shift accumulator + $Y$ register.

• Advantage: ~N/2 partial products vs N for array multiplier.

2. Structure of Booth Multiplier with Example

• Example: 4-bit × 4-bit ($Y \times X$).

  1. Booth Encoder/Selector: For each of 4 cycles, selects {0, Y, -Y} based on 2-bit Booth code.

  2. Partial Product Generation: -Y generated by inverting Y and adding 1 (via initial carry-in).

  3. Accumulator: 8-bit (or 9-bit) register. Each cycle: Add selected PP to accumulator, then arithmetic right shift (accumulator & Y register).

  4. Control: Shift counter, Booth decoder.

  [!TIP] Diagram:

  DiagramCANVAS: Booth multiplier block diagram: Booth decoder, PP generation (Y, -Y, 0), 8-bit accumulator with adder, shift registers.

  • Example Calculation: $$\displaystyle Y=1101 $$ (-3 in 2's complement), $$\displaystyle X=1011 $$ (-5). Show Booth codes (11, 10, 01, 10) and resulting PP sequence.

X. Design Methodologies and Libraries

A. Pipelining for Performance Enhancement

• Concept: Break long combinational paths into shorter stages by inserting pipeline registers (FFs).

• Throughput: Increases (one result per clock cycle, after fill).

• Latency: Increases (total cycles to complete one operation).

• Clock Frequency: Increases (determined by slowest stage delay).

• Trade-offs: Area (extra FFs), Power (more clocked nodes), Design complexity (balancing stages, handling hazards).

• Stage Balancing: Aim for equal delay in all stages to maximize throughput.

B. Cell Libraries: Standard Cells, Characterization, and Usage

• Standard Cell Library: Collection of pre-characterized, pre-layout CMOS cells (INV, NAND2, NOR2, FF, etc.) with fixed height (site-based).

• Characterization: For each cell, under various conditions ($$\displaystyle V_{DD} $$, temp, load):

  • Timing: $$\displaystyle t_{pLH}, t_{pHL}, t_{su}, t_h, t_{cQ} $$ (often as lookup tables or polynomial models).

  • Power: Leakage, internal, switching power.

  • Area: $W \times H$.

  • Input Capacitance: $$\displaystyle C_{in} $$ for each pin.

• Usage in Design Flow:

  1. Synthesis: Map RTL netlist to library cells.

  2. Place & Route: Place cells, connect with metal.

  3. Timing/Power Analysis: Use library models to verify constraints.

  [!TIP] Key Point: Standard cells enable automated physical design. Library quality (timing models, variety) directly impacts final design performance and area.

XI. Programmable Logic: FPGA

A. Building Block Architecture

1. Configurable Logic Blocks (CLBs)

• Function: Implement user logic (combinational + sequential).

• Typical Structure:

  • Look-Up Tables (LUTs): Small SRAM-based truth tables (e.g., 4-input LUT = 16-bit RAM). Implement any 4-input Boolean function.

  • Flip-Flops: One or two FFs per LUT output for pipelining.

  • Multiplexers: Configure LUT inputs, select between LUT output or FF output.

  • Fast Carry Chains: Dedicated logic for efficient adders.

  • Diagram:

    DiagramCANVAS: CLB slice showing 4-input LUT, FF, MUXes, carry chain connections.

2. Input/Output Blocks (IOBs)

• Function: Interface between internal logic and package pins.

• Features: Programmable drive strength, slew rate, pull-up/pull-down resistors, I/O standard compatibility (LVCMOS, LVDS, etc.), bidirectional control.

3. Programmable Interconnect

• Routing Resources: Hierarchical network of wires (local, intermediate, global) connected via programmable switches.

• Switch Matrix: At intersection of horizontal and vertical channels. Contains pass transistors or multiplexers controlled by configuration bits.

• Goal: Provide flexible connectivity while managing RC delay and area.

B. Programming Technologies

[!TIP] Comparison: SRAM = flexible, high static power. Antifuse/Flash = low power, non-volatile, but less flexible or slower.

XII. Design Representation and Abstraction

A. Stick Diagrams: Purpose and Creation

• Purpose: Quick, technology-independent visualization of layout connectivity and layer assignment.

• Creation Rules (Color Code):

  • Diffusion (Active): Blue (NMOS), Red (PMOS) or single color.

  • Poly: Yellow.

  • Metal1: Green.

  • Metal2: Orange.

  • Contacts/Vias: Black squares.

• Steps:

  1. Draw diffusion regions for transistors (shared where possible).

  2. Draw poly lines crossing diffusion to form gates.

  3. Connect sources/drains with metal1 (show contacts).

  4. Show pin connections (usually metal2).

  5. Ensure no design rule violations (min spacing, overlap).

B. Relationship between Schematic, Stick Diagram, and Layout

1. Schematic: Logical/electrical view. Shows transistors, gates, wires, and connectivity. Technology-independent.

2. Stick Diagram: Abstract physical view. Shows relative placement of transistors and routing layers. Design rule check (DRC) at conceptual level. Bridge between schematic and layout.

3. Layout (Mask): Detailed physical view. Actual geometric shapes with exact dimensions (λ or μm). DRC-clean, used for mask generation.

• Flow: Schematic → Stick Diagram (planning) → Layout (detailed implementation) → Verification (DRC, LVS, ERC).

  [!TIP] LVS (Layout vs. Schematic): Must match exactly. Stick diagram helps catch connectivity errors early.