VLSI circuits and systems (EX-803 (C)) - Unit 1 Short Notes

UNIT 1: MOS TRANSISTOR FUNDAMENTALS AND SCALING

Electrical Properties of MOS Transistor

• Threshold Voltage ($$\displaystyle V_{th} $$): Minimum gate-to-source voltage required to create a conducting channel. Determined by oxide thickness ($$\displaystyle T_{ox} $$), substrate doping, and work function difference.

  $$\displaystyle V_{th} = V_{FB} + 2\phi_F + \frac{\sqrt{2q\epsilon_{si} N_a 2\phi_F}}{C_{ox}} $$

• Mobility ($\mu$): Carrier drift velocity per unit electric field. $$\displaystyle \mu_n > \mu_p $$ for electrons vs. holes. Degrades with high vertical field (surface scattering).

• Oxide Capacitance ($$\displaystyle C_{ox} $$): $$\displaystyle C_{ox} = \frac{\epsilon_{ox}}{T_{ox}} $$. Directly impacts gate control and $$\displaystyle I_{ds} $$.

• Current-Voltage Characteristics:

  • Triode/Linear Region ($$\displaystyle V_{gs} > V_{th} $$, $$\displaystyle V_{ds} < V_{gs} - V_{th} $$): $$\displaystyle I_{ds} = \mu_n C_{ox} \frac{W}{L} \left[ (V_{gs} - V_{th})V_{ds} - \frac{V_{ds}^2}{2} \right] $$

  • Saturation Region ($$\displaystyle V_{gs} > V_{th} $$, $$\displaystyle V_{ds} \ge V_{gs} - V_{th} $$): $$\displaystyle I_{ds} = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{gs} - V_{th})^2 (1 + \lambda V_{ds}) $$

    • $\lambda$: Channel Length Modulation (CLM) parameter. Models output conductance due to depletion region extension.

• Subthreshold Conduction: Weak inversion current when $$\displaystyle V_{gs} < V_{th} $$. $$\displaystyle I_{ds} \propto e^{(V_{gs} - V_{th})/nV_T} $$, where $n$ is subthreshold slope factor. Critical for low-power design leakage.

Need for Scaling in VLSI

• Drivers: Increase transistor density (more functionality/chip), improve performance (higher speed, lower delay), reduce cost (more chips/wafer), lower power (smaller capacitance, lower voltage).

• Dennard Scaling (1974): Proposed proportional scaling of all dimensions and voltages to maintain constant electric field.

  • $$\displaystyle L, W, T_{ox} \rightarrow \frac{1}{S} $$; $$\displaystyle V_{dd} \rightarrow \frac{1}{S} $$; $$\displaystyle N_a \rightarrow S $$

  • Result: Power density constant, delay $\propto 1/S$, frequency $\propto S$.

Scaling Principles and Models

• Short-Channel Effects (SCE) (as $L$ shrinks):

  • Drain-Induced Barrier Lowering (DIBL): High $$\displaystyle V_{ds} $$ lowers $$\displaystyle V_{th} $$, increases subthreshold leakage.

  • Velocity Saturation: Carrier velocity saturates at high $E$-field, reducing current gain from scaling ($$\displaystyle I_{ds} \propto (V_{gs}-V_{th}) $$ not $$\displaystyle (V_{gs}-V_{th})^2 $$).

  • Other SCE: Punch-through, increased leakage, threshold voltage roll-off.

Fundamental Units of CMOS Inverter

• Structure: Pull-up network (PUN, PMOS) in parallel to pull-down network (PDN, NMOS). Inputs complementary.

• Voltage Transfer Characteristic (VTC): Plot of $$\displaystyle V_{out} $$ vs $$\displaystyle V_{in} $$.

  • Switching Threshold ($$\displaystyle V_M $$): $$\displaystyle V_{in} $$ where $$\displaystyle V_{in} = V_{out} $$. For symmetric inverter ($$\displaystyle \beta_n = \beta_p $$), $$\displaystyle V_M \approx \frac{V_{dd}}{2} $$.

  • Noise Margins:

    • NM_L (Low): $$\displaystyle V_{IL} - V_{OL} $$ (max noise in LOW state)

    • NM_H (High): $$\displaystyle V_{OH} - V_{IH} $$ (max noise in HIGH state)

    • Where $$\displaystyle V_{IL} $$ (max $$\displaystyle V_{in} $$ for valid LOW), $$\displaystyle V_{IH} $$ (min $$\displaystyle V_{in} $$ for valid HIGH).

  • Ideal: High gain in transition region, sharp switching.

• Transistor Sizing: For balanced rise/fall times, $$\displaystyle \frac{(W/L)_p}{(W/L)_n} \approx \frac{\mu_n}{\mu_p} \approx 2-3 $$ (since PMOS mobility is ~2-3x lower).

[!TIP] Exam Focus: Derive $$\displaystyle V_M $$ for symmetric inverter. Explain how sizing affects VTC and noise margins. Relate SCE to inverter characteristics (e.g., DIBL reduces noise margins).

UNIT 2: CMOS LOGIC DESIGN AND LAYOUT

Layout Design Rules

• Purpose: Ensure manufacturability, prevent shorts/opens, guarantee electrical connectivity.

• Types:

  • Lambda ($\lambda$)-based Rules: All dimensions in multiples of $\lambda$ (half the minimum feature size). Process-independent. e.g., Minimum width = $2\lambda$, Minimum spacing = $2\lambda$.

  • Micron-based Rules: Absolute dimensions in $\mu m$. Process-specific.

• Key Rules:

  • Minimum Width: Narrowest wire/transistor channel allowed.

  • Minimum Spacing: Minimum distance between two same-layer features.

  • Enclosure/Overlap: Diffusion must be enclosed by poly (for transistor gate). Contact must be enclosed by diffusion/poly.

  • Extension: Diffusion/poly must extend beyond contact for alignment tolerance.

  • Well/Substrate Contacts: Placement rules for substrate ties.

Layout of Basic Gates

• NAND Gate (2-input):

  • PDN: NMOS in series.

  • PUN: PMOS in parallel.

  • Layout: Shared diffusion for series NMOS; separate diffusion for parallel PMOS. Inputs $A$, $B$ from poly; output from metal1 contact.

  • Stick Diagram:

    DiagramSEARCH: "CMOS NAND gate stick diagram"
    - Use colors: green (diffusion), red (poly), blue (metal1), yellow (contact).

• NOR Gate (2-input):

  • PDN: NMOS in parallel.

  • PUN: PMOS in series.

  • Layout: Shared diffusion for parallel NMOS; series PMOS require separate diffusion connected by poly.

  • Stick Diagram:

    DiagramSEARCH: "CMOS NOR gate stick diagram"

[!TIP] Common Pitfall: Forgetting that series PMOS need separate diffusion regions (cannot share like NMOS in NAND). Always verify pull-up/pull-down networks are duals.

Combinational Circuit Design using CMOS

• Design Methodology:

  1. Derive pull-down network (PDN) from logic expression (transistors in parallel for OR, series for AND).

  2. Obtain pull-up network (PUN) as dual of PDN (swap series/parallel, replace NMOS with PMOS).

  3. Ensure no static current path (PDN and PUN never ON simultaneously for any input).

• Complex Gates (AOI/OAI):

  • AOI21 (AND-OR-Invert): $$\displaystyle Y = \overline{(A \cdot B) + C} $$. PDN: Parallel path (A&B series) and single C. PUN: Dual.

  • OAI21 (OR-AND-Invert): $$\displaystyle Y = \overline{(A+B) \cdot C} $$. PDN: Series path (A|B parallel) and single C. PUN: Dual.

  • Advantage: Fewer transistors than decomposed NAND/NOR, faster, less capacitance.

• Transistor Sizing for Balanced Delay: Size transistors in series to maintain effective resistance. For $n$ series NMOS, each $W$ scaled by $n$ to match single NMOS resistance.

Pass Transistor Logic (PTL)

• Basic Gate: Uses MOSFETs as switches to pass signals. Input drives gate, signal passes through source-drain.

  • Example: Transmission gate XOR: $$\displaystyle Y = A \oplus B $$ using 4 transistors (2 transmission gates).

• Advantages:

  • Reduced transistor count vs. static CMOS.

  • Lower input capacitance, potentially higher speed.

• Disadvantages:

  • Voltage Drop: NMOS pass transistor cannot pass full $$\displaystyle V_{dd} $$ (threshold loss $$\displaystyle V_{th} $$). PMOS passes full rail but slower.

  • Charge Sharing: Floating nodes can discharge through multiple paths.

  • Static Power: May have DC paths if not carefully designed.

  • Poor Noise Margins: Weak high-level output.

• Comparison with Static CMOS:

  | Feature | Static CMOS | PTL | | :--- | :--- | :--- | | Static Power | Near zero | Can be non-zero (leakage paths) | | Noise Margin | High | Low (due to voltage drop) | | Transistor Count | Higher | Lower | | Area | Larger | Smaller | | Fan-out Drive | Full rail-to-rail | Degraded (NMOS pass) |

Transmission Gate

• Structure: Parallel combination of NMOS (gate controlled by $C$) and PMOS (gate controlled by $\overline{C}$). Both controlled by complementary signals.

  • When $$\displaystyle C=1 $$, NMOS ON, PMOS OFF → conducts.

  • When $$\displaystyle C=0 $$, NMOS OFF, PMOS ON → conducts.

• Applications:

  • Multiplexers (2:1 MUX): Select between two inputs.

  • Bidirectional Switch: Bidirectional signal flow.

  • Latch Design: Core element for level-sensitive storage (e.g., D-latch).

• Advantages over Single MOSFET Pass:

  • Full Voltage Swing: Passes both logic 0 and 1 without threshold loss.

  • Symmetrical Resistance: Similar ON resistance for both logic levels.

  • Better Noise Immunity.

[!TIP] Exam Focus: Draw and explain 2-input MUX using transmission gates. Compare PTL XOR vs. static CMOS XOR (transistor count, performance). Explain why transmission gate solves NMOS pass transistor voltage drop problem.

UNIT 3: TIMING ANALYSIS AND INTERCONNECT DELAY

Elmore's Constant and Delay Model

• Definition: First-order RC tree delay approximation. For a linear RC network, Elmore delay at node $x$ is the sum of $R \cdot C$ products of all capacitors to ground multiplied by resistance of path from source to that capacitor.

  $$\displaystyle t_{pd} \approx 0.69 \cdot \tau_{Elmore} $$, where $$\displaystyle \tau_{Elmore} = \sum_{i} R_{path(i)} \cdot C_i $$

• Calculation for Simple RC Ladder:

  • For chain: $$\displaystyle R_1-C_1-R_2-C_2-...-R_n-C_n $$ (output at $$\displaystyle C_n $$):

$$\tau_{Elmore} = R_1(C_1+C_2+...+C_n) + R_2(C_2+...+C_n) + ... + R_n C_n$$

• Assumptions: Linear resistors, grounded capacitors, step input, output at 50% of final value.

Elmore Delay for CMOS Inverter

• Model: Input driver (PMOS/NMOS with on-resistance $$\displaystyle R_{eqp}, R_{eqn} $$) driving load capacitance $$\displaystyle C_L $$ (includes gate capacitance of next stage + interconnect).

• Propagation Delays:

  • $$\displaystyle t_{pHL} $$ (HIGH→LOW, NMOS pulls down):

$$\tau_{HL} \approx R_{eqn} \cdot C_L \quad \Rightarrow \quad t_{pHL} \approx 0.69 \cdot R_{eqn} \cdot C_L$$

*   **$$\displaystyle t_{pLH} $$** (LOW→HIGH, PMOS pulls up):

$$\tau_{LH} \approx R_{eqp} \cdot C_L \quad \Rightarrow \quad t_{pLH} \approx 0.69 \cdot R_{eqp} \cdot C_L$$

*   **Average Propagation Delay**: $$\displaystyle t_p = \frac{t_{pLH} + t_{pHL}}{2} \approx 0.69 \cdot \frac{R_{eqn} + R_{eqp}}{2} \cdot C_L $$

• Impact:

  • $$\displaystyle C_L $$ ↑ → Delay ↑ (includes fan-out + wire capacitance).

  • $$\displaystyle R_{eq} $$ ↑ (from longer $L$ or lower mobility) → Delay ↑.

  • Sizing: Increase $W$ ↓ $$\displaystyle R_{eq} $$ ↓ Delay, but ↑ $$\displaystyle C_{gate} $$ (trade-off).

Clock Distribution in Synchronous Design

• Requirements: Low Skew (arrival time difference at registers), Low Latency (min delay from source), High Clock Rate (min jitter), Low Power.

• Techniques:

  1. H-Tree: Symmetric binary tree. Guarantees zero skew at leaves if all branches identical. Area-intensive, not load-balanced.

  2. Clock Grid: Mesh of metal lines. Low skew, high capacitance → high power. Used in high-performance CPUs.

  3. Clock Buffers/Inverters: Insert buffers along long lines to drive load and balance delay. Deskewing: Adjust buffer sizes/locations to minimize skew.

  4. Clock Gating: Insert enable-controlled gates (e.g., latch-based) to stop clock to idle blocks → dynamic power reduction.

  5. Clock Tree Synthesis (CTS): Automated tool step to build balanced clock tree with zero/controlled skew.

[!TIP] Exam Focus: Derive Elmore delay for 2-inverter chain. Compare H-tree vs. grid. Explain clock gating implementation (AND gate with enable) and its timing implications.

UNIT 4: SEQUENTIAL CIRCUIT DESIGN

Design Methodology for Latches and Flip-Flops

• Latch: Level-sensitive. Transparent when clock = 1 (or 0), opaque otherwise. Built from static CMOS or transmission gates.

  • SR Latch: Cross-coupled NOR/NAND. Asynchronous set/reset.

  • D Latch: $D \to Q$ when clock=1. Uses 2:1 MUX (transmission gate) or gated D-latch (feedback).

• Flip-Flop: Edge-triggered. Changes state only at clock edge (rising/falling). Master-slave or pulse-triggered.

  • Master-Slave D Flip-Flop: Two latches (master, slave) in series, clocked with complementary phases (e.g., master on $$\displaystyle \phi=1 $$, slave on $$\displaystyle \phi=0 $$). Avoids race-around condition in feedback latches.

  • Pulse-Triggered: Single latch with conditional feedback, triggered by short clock pulse.

Master-Slave Edge-Triggered Register

• Operation Principle:

  1. Positive Clock Phase: Master transparent, slave opaque. Input $D$ propagates to master output $M$.

  2. Negative Clock Phase: Master opaque, slave transparent. $M$ propagates to slave output $Q$.

  • Result: $Q$ updates to $D$ value only at falling edge (for negative-edge master-slave).

• Implementation using Transmission Gates:

  • Master/Slave each: D-latch using 2 transmission gates (for 2:1 MUX) + 2 inverters (for feedback).

  • Clock phases: $\phi$ and $\overline{\phi}$.

• Timing Diagram: Shows $D$, $\phi$, $M$, $Q$. $Q$ changes only at falling edge of $\phi$.

• Race-Around Condition: Problem in single latch with feedback: if clock pulse width > latch delay, input can race through multiple times. Solved by master-slave (two transparent periods separated by opaque periods).

[!TIP] Exam Focus: Draw master-slave D flip-flop using transmission gates. Explain timing with waveform. Contrast with transparent latch. Why is master-slave edge-triggered?

UNIT 5: ARITHMETIC CIRCUITS

Carry Look-Ahead Adder (CLA)

• Principle: Generate ($$\displaystyle G_i $$) and Propagate ($$\displaystyle P_i $$) signals to compute carry in parallel, reducing carry propagation delay from $O(n)$ (ripple) to $O(\log n)$.

  • $$\displaystyle G_i = A_i \cdot B_i $$ (carry generated at bit $i$)

  • $$\displaystyle P_i = A_i \oplus B_i $$ (carry propagated from bit $i$)

• Carry Equations:

  • $$\displaystyle C_1 = G_0 + P_0 C_0 $$

  • $$\displaystyle C_2 = G_1 + P_1 G_0 + P_1 P_0 C_0 $$

  • $$\displaystyle C_3 = G_2 + P_2 G_1 + P_2 P_1 G_0 + P_2 P_1 P_0 C_0 $$

  • $$\displaystyle C_i = G_{i-1} + P_{i-1} G_{i-2} + ... + (\prod_{j=0}^{i-1} P_j) C_0 $$

• Group Propagate/Generate (for block CLA):

  • $$\displaystyle P_{i:j} = P_i \cdot P_{i-1} \cdot ... \cdot P_j $$

  • $$\displaystyle G_{i:j} = G_i + P_i G_{i-1} + ... + (\prod_{k=j}^{i} P_k) G_{j-1} $$

• Block Diagram:

  DiagramSEARCH: "4-bit carry look ahead adder block diagram"
  - Shows PG logic, carry logic, sum logic ($$\displaystyle S_i = P_i \oplus C_i $$).

• Speed vs. Area Trade-off: Fast (logarithmic delay) but large area and complex wiring due to many product terms.

Carry Bypass Adder (CBA)

• Principle: For each block (e.g., 4-bit), bypass carry if all $$\displaystyle P_i=1 $$ (no generate). Otherwise, use ripple within block.

  • Bypass Logic: $$\displaystyle Bypass = P_0 \cdot P_1 \cdot ... \cdot P_{k-1} $$ (for k-bit block). If $$\displaystyle Bypass=1 $$, $$\displaystyle C_{out} = C_{in} $$.

• 16-bit Design:

  • Divide into four 4-bit blocks.

  • Each block has internal ripple chain + bypass logic.

  • Carry chain: $$\displaystyle C_1 $$ computed from block0, then block1 uses $$\displaystyle C_1 $$ or bypasses based on $$\displaystyle P_{0:3} $$, etc.

• Features:

  • Reduced carry delay for low-activity inputs (many propagates).

  • Variable block size trade-off: larger blocks → more bypass opportunities but longer internal ripple.

  • Area: Less than CLA, more than ripple.

• Comparison:

  | Adder Type | Delay | Area | Best Case | Worst Case | | :--- | :--- | :--- | :--- | :--- | | Ripple Carry | $O(n)$ | Small | - | All generates | | CLA | $O(\log n)$ | Large | - | - | | CBA | $O(\sqrt{n})$ | Medium | All propagates (bypass) | All generates (ripple) |

Booth Multiplier

• Booth Encoding: Reduces number of partial products by re-coding signed multiplicand bits. Radix-2 (single overlap) or Radix-4 (double overlap, more common).

  • Radix-4 Booth: Examine 3 bits ($$\displaystyle B_{2i+1}, B_{2i}, B_{2i-1} $$) with overlap. Generate control signals:

    • $00\overline{0}$ or $11\overline{1}$ → 0

    • $00\overline{1}$ or $11\overline{0}$ → $+Y$

    • $01\overline{0}$ or $10\overline{1}$ → $+2Y$ (shift left 1)

    • $01\overline{1}$ or $10\overline{0}$ → $-Y$

    • $0\overline{0}1$ or $1\overline{1}0$ → $-2Y$

• Structure:

  1. Booth Encoder/Decoder: Generates control signals for each 3-bit group.

  2. Partial Product Generator: For each group, outputs $0$, $\pm Y$, $\pm 2Y$ (shifted).

  3. Carry-Save Adder (CSA) Array: Adds partial products in carry-save form (sum & carry) to avoid carry propagation until final stage.

  4. Final Carry-Propagate Adder (e.g., CLA): Adds final sum and carry to produce product.

• Example (Radix-2, 4-bit): Multiplicand $$\displaystyle Y = 1101 $$ (-3), Multiplier $$\displaystyle X = 1011 $$ (-5). After Booth recoding (with sign extension), generate partial products, sum with CSA.

[!TIP] Exam Focus: Draw 4-bit CLA block diagram, write carry equations. Explain Booth radix-4 encoding table. For 8-bit multiplier, show partial product reduction using CSA array.

UNIT 6: DESIGN AUTOMATION AND METHODOLOGIES

Stick Diagrams

• Purpose: Symbolic, color-coded representation for early layout planning and area estimation. Quick to draw, shows connectivity and layer stacking.

• Color Coding (Standard):

  • Green: Diffusion (n+ / p+)

  • Red: Polysilicon (poly)

  • Blue: Metal1 (m1)

  • Yellow: Contact/via

  • Brown: Metal2 (m2), etc.

• Rules:

  • Wire crosses = no connection (unless via shown).

  • Diffusion + poly crossing = transistor (gate at intersection).

  • Contact = connection between layers (e.g., diffusion to m1).

• Conversion to Layout: Replace sticks with actual shapes respecting design rules (widths, spacings).

Cell Libraries

• Components:

  • Standard Cells: Pre-characterized, height-fixed, abuttable cells (inverters, NAND, NOR, XOR, flip-flops, adders, buffers).

  • I/O Cells: Pad rings, drivers, ESD protection.

  • Empty/Spacer Cells: For filler.

• Characterization (per cell, per process corner, voltage, temperature):

  • Timing: $$\displaystyle t_{pLH} $$, $$\displaystyle t_{pHL} $$, rise/fall slew, setup/hold time (for FFs).

  • Power: Leakage, internal, switching.

  • Area: Width, height.

  • Electrical: Input capacitance, pin capacitance.

• Use in ASIC Flow:

  1. Synthesis: Map RTL to library cells (optimize for timing/area/power).

  2. Placement: Place cells on die.

  3. Routing: Connect cells with interconnect.

  4. Timing Analysis: Verify against library timing models (often NLDM - non-linear delay model).

Pipeline Design

• Principle: Break long combinational logic path into shorter stages separated by registers (flip-flops). Each stage operates on different data simultaneously.

• Benefits:

  • Increased Throughput: One result per clock cycle (after fill).

  • Higher Clock Frequency: Stage delay < cycle time.

  • Better Area-Performance Trade-off: Can balance stages.

• Challenges:

  • Pipeline Hazards: Structural (resource conflict), Data (RAW, WAR, WAW), Control (branch misprediction).

  • Clock Skew: Must be minimized across all registers.

  • Stage Balancing: Critical for max frequency. Pipeline bubbles/stalls if stages unbalanced.

  • Increased Latency: More registers → more clock cycles for one computation.

• Implementation: Insert registers at boundaries. Use pipelined registers (with enable) for data transfer control.

[!TIP] Exam Focus: Draw stick diagram for simple CMOS gate (e.g., NAND). List library characterization parameters. Explain pipeline vs. non-pipeline performance (throughput, latency). What is pipeline bubble?

UNIT 7: FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs)

FPGA Building Block Architecture

• Configurable Logic Block (CLB) / Logic Element (LE):

  • Lookup Table (LUT): $k$-input LUT implements any $k$-input Boolean function. $$\displaystyle k=4,5,6 $$ common. SRAM-based.

  • Flip-Flop: Optional register after LUT output for sequential logic.

  • Carry Chain: Dedicated fast carry logic for adders (often in CLB).

  • Multiplexers: For LUT input selection, mode control.

• Interconnect Resources:

  • Routing Channels: Horizontal/vertical wires between CLB rows/columns.

  • Switch Boxes: At channel intersections. Programmable switches (pass transistors, tri-states, muxes) connect wires.

  • Long Lines: Global wires for clocks, resets, high-fanout signals.

• I/O Blocks (IOBs): Programmable I/O standards (LVCMOS, LVDS), drive strength, slew rate, pull-ups. Connect internal logic to package pins.

• Architecture Types: Island-style (CLBs in rows/cols, channels between) vs. Sea-of-Gates.

Programming Technologies for FPGAs

• Comparison:

  • SRAM: Dominant (Xilinx, Intel). Flexible, high density, but needs external config memory, susceptible to radiation (SEU).

  • Antifuse: Actel (Microsemi). High performance, secure, radiation-hardened, but one-time.

  • Flash: Lattice, Microchip. Lower power, instant-on, secure, moderate density.

  • FeRAM: Rare, emerging.

[!TIP] Exam Focus: Draw block diagram of FPGA showing CLB, routing, IOB. Compare SRAM vs. Antifuse in table. Why is carry chain important in CLB? What is LUT size trade-off?