Hardware Security (CY-801) - Unit 4 Short Notes

1. Finite Field Arithmetic & Implementation

Construction of Finite Fields

• Prime Fields (GF(p)): Field with prime number of elements p. Arithmetic is modulo p.

• Extension Fields (GF(2^m)): Field with 2^m elements, constructed using an irreducible polynomial f(x) of degree m over F₂.

  • Example: GF(4) using f(x) = x² + x + 1 over F₂:

    1. Elements: {0, 1, α, α+1} where α is a root of f(x), so α² = α + 1 (since α² + α + 1 = 0).

    2. Addition: Coefficient-wise XOR (e.g., α + (α+1) = 1).

    3. Multiplication: Multiply polynomials mod f(x) (e.g., α * α = α² ≡ α + 1).

• Representation: Polynomial basis {1, α, α², ...} or normal basis for efficient hardware.

Finite Field Multipliers (GF(2^m))

• Architectures:

  • Combinational: Fully parallel, high speed, large area.

  • Sequential: Bit-serial, low area, high latency.

  • Semi-serial: Trade-off between area and speed.

• Optimization Metrics:

  • Area: Gate count, LUT usage in FPGA.

  • Speed: Critical path delay (ns).

  • Power: Dynamic/static power consumption.

• Domain-Specific: Use shift-register based multipliers for GF(2^m) leveraging XOR and AND gates with reduction modulo irreducible polynomial.

Polynomial Identity Testing

• Problem: Given arithmetic circuit C with inputs a₁,...,aₙ and constants from field F, check if computed polynomial P(a₁,...,aₙ) is identically zero.

• Schwartz-Zippel Lemma:

  Randomly assign inputs from a set S ⊂ F. If P is non-zero, probability of evaluating to zero is ≤ deg(P)/|S|.

$$\boxed{\Pr[P(x_1,...,x_n)=0] \leq \frac{\deg(P)}{|S|}}$$

• Algorithm:

  1. Pick random rᵢ ∈ S for each input.

  2. Evaluate C(r₁,...,rₙ).

  3. If zero → likely identical zero (with high probability); else → definitely not.

• Applications: Formal verification of arithmetic circuits, detection of hardware trojans.

[!TIP]

Exam Focus: Be ready to construct GF(4) step-by-step. For multipliers, compare architectures in a table. Schwartz-Zippel is a probabilistic method—state the error bound clearly.

2. Field-Programmable Gate Array (FPGA) Security

Accuracy Issues in FPGA Implementations

• Process Variation: Transistor threshold voltage mismatch → timing skew, power variation.

• Timing Inaccuracies: Setup/hold time violations due to routing delays, clock distribution skew.

• Impact on Security Circuits: Cryptographic cores (AES, RSA) become vulnerable to timing attacks or fault injections if margins are tight.

Precision Enhancement Techniques

• Calibration Methods:

  • Design-time: Static timing analysis with worst-case corners.

  • Run-time: On-chip sensors (ring oscillators) to measure delay, adjust clock frequency.

• Redundancy & Error Correction:

  • Configuration Redundancy: Triple Modular Redundancy (TMR) for flip-flops and routing.

  • Error Correction Codes (ECC): For configuration memory (e.g., CRC-based scrubbing).

• Design-time vs Run-time:

  • Design-time: Conservative constraints, robust layout.

  • Run-time: Dynamic reconfiguration, adaptive clocking.

[!TIP]

Common Pitfall: Don’t confuse FPGA accuracy issues with general VLSI variation—emphasize configurable logic and routing specifics.

3. Physical Unclonable Functions (PUFs)

Fundamentals of PUFs

• Definition: Hardware structure that maps challenges C to responses R via inherent manufacturing variations, producing a unique, unclonable fingerprint.

• Core Properties:

  • Unclonability: Impossible to duplicate identical PUF physically.

  • Tamper-Evidence: Physical probing destroys characteristics.

• Common Types:

  • SRAM PUF: Startup bits of SRAM cells (due to imbalance).

  • Arbiter PUF: Race condition between two symmetric delay lines; output depends on which signal arrives first.

  • Ring Oscillator (RO) PUF: Frequency differences between pairs of ROs; encode as 0/1 based on which is faster.

PUF Security Parameters

• Reliability: Consistency of responses under varying conditions (temp, voltage). Measured by intra-chip Hamming distance.

• Uniqueness: Distinguishability across chips. Measured by inter-chip Hamming distance (~50% for ideal).

• Randomness: Uniformity of response bits (balanced 0s/1s). Tested by NIST suite.

• Entropy: Min-entropy H_min = -log₂(max_probability) of response distribution.

PUF Attacks

• Modeling Attacks:

  • ML-based: Train predictor (e.g., SVM, logistic regression) on collected Challenge-Response Pairs (CRPs).

  • Example: Arbiter PUF is linear in delay differences → vulnerable to linear regression.

• Invasive Attacks: Decapsulation, nano-probing to extract internal structure → clone PUF.

• Non-Invasive Attacks:

  • Side-channel: Monitor power/EM during PUF operation to infer delays.

  • Manipulation: Control voltage/temperature to bias responses.

Design Techniques for Quality Enhancement

• Circuit-Level:

  • Balanced Delay Lines: For Arbiter PUF, use symmetrical layout, dummy buffers.

  • Temperature/Voltage Compensation: Calibration circuits.

• Error Correction:

  • ECC: BCH codes, concatenated codes to correct noisy responses.

  • Fuzzy Extractors: Helper data algorithms for secure key generation.

• Challenge-Response Transformation:

  • Obfuscation: Apply cryptographic hash to challenges to prevent modeling.

  • XOR of multiple PUFs: Increase non-linearity.

Model Building Attacks on PUFs

• Workflow:

  1. Collect large set of CRPs.

  2. Extract features (e.g., delay differences for Arbiter PUF).

  3. Train ML model to predict response for new challenge.

• Example: Arbiter PUF with n stages → response is sign of linear combination of stage delays. Logistic regression can learn weights with enough CRPs.

• Limitations: Requires many CRPs, may fail for non-linear PUFs (e.g., XOR Arbiter PUF).

Hardware Piracy Prevention Using PUFs

• IP Protection:

  • Bind IP core activation to PUF response → only genuine devices unlock.

• Device Fingerprinting:

  • Use PUF response as unique ID for authentication.

• Secure Key Generation:

  • Derive cryptographic keys from PUF responses (with ECC).

• Overbuilding Prevention:

  • Manufacturer cannot clone PUF → unauthorized copies fail authentication.

[!TIP]

High-Yield: Always link PUF design techniques (e.g., balancing, ECC) to countering specific attacks (modeling, reliability). For hardware piracy, emphasize binding and authentication.

4. Side-Channel Attacks (SCA)

Introduction & Classification

• Definition: Exploit physical leakages (power, time, EM) from hardware during computation to infer secrets.

• Categories:

  • Passive: Monitor leakages (e.g., power analysis).

  • Active: Manipulate device (e.g., fault injection—covered separately).

  • Single-Vector: One side-channel source.

  • Multi-Vector: Combine multiple sources (power + EM).

Types of Side-Channel Attacks

• Timing Attacks:

  • Measure execution time variations due to data-dependent branches/memory accesses.

  • Cache Attacks:

    • Prime+Probe: Flush cache, wait, probe for eviction sets.

    • Flush+Reload: Flush shared memory, reload to measure access time.

    • Evict+Time: Evict target set, measure time for access.

• Power Analysis:

  • Simple Power Analysis (SPA): Visual inspection of power traces to identify operations (e.g., RSA square-multiply).

  • Differential Power Analysis (DPA): Statistical correlation between power consumption and hypothetical intermediate values (e.g., key bytes).

• Electromagnetic (EM) Attacks: Similar to power but with spatial resolution; probe near chip.

Case Study: DES Side-Channel Attack

• Vulnerability: DES S-boxes are key-dependent; Hamming weight of S-box output correlates with power.

• Attack Steps:

  1. Record power traces for many plaintexts.

  2. For each possible key byte k, compute intermediate value S-box(P ⊕ k).

  3. Hypothesize power model (e.g., Hamming weight of intermediate).

  4. Compute correlation between modeled and actual power across traces.

  5. Key byte with highest correlation is correct.

• Key Recovery: Repeat for all 8 S-boxes → full 56-bit key.

Countermeasures Against SCA

• Hiding:

  • Random Delays: Insert dummy operations.

  • Power Balancing: Dual-rail precharge, current flattening circuits.

  • Noise Injection: Add random circuitry to mask consumption.

• Masking:

  • Boolean Masking: Split secret s into s₁ ⊕ s₂ = s; operate on shares.

  • Arithmetic Masking: Modulo addition (e.g., s + r mod p).

  • Threshold Implementation: Ensure each share is independent and uniform.

• Algorithmic:

  • Constant-Time: Data-independent memory accesses/branches.

  • Secure S-boxes: Pre-compute masked S-boxes or use bitslicing.

• Hardware:

  • Shielding: EM/RF shielding cans.

  • Dedicated Secure Cells: Isolated crypto engines with noise generators.

[!TIP]

DES Case Study is Crucial: Know the correlation DPA step. Countermeasures: masking (first-order secure) vs hiding (reduce signal-to-noise). Cache attacks are a subset of timing attacks—focus on Prime+Probe/Flush+Reload.

5. Fault Attacks

Fault Injection Techniques

• Voltage Glitching: Sudden drop/increase in VDD to cause timing errors.

• Clock Glitching: Shorten clock period to skip cycles.

• Laser Fault Injection: Focused laser beam to induce bit flips in SRAM/registers.

• Temperature/Radiation: Extreme temps or alpha particles cause soft errors.

Fault Tolerance Architectures in Cryptography

• Redundant Execution:

  • Dual Modular Redundancy (DMR): Two copies, compare outputs.

  • Triple Modular Redundancy (TMR): Three copies, majority vote.

• Error Detection & Correction:

  • Parity/Checksum: Detect errors in intermediate states.

  • Residue Codes: Modulo check for arithmetic operations.

• Secure Fault Recovery:

  • Verification: Re-compute with different representation (e.g., masked vs unmasked).

  • Architecture:

    
    [Input] → [Crypto Core 1] → |
    
                      |→ [Comparator] → [Valid Output]
    
    [Input] → [Crypto Core 2] → |
    
    

    If mismatch → fault detected, discard output.

• DiagramCANVAS: Show TMR in AES round: three parallel S-box/Shift/Add layers, voter at output, with control logic to reset on fault.

[!TIP]

Cache Attacks are typically under SCA, but if exam lists separately, note they exploit timing, not faults. Fault attacks induce errors; SCA observes leakage.

6. Advanced Implementation & Verification Techniques

Domain-Specific Hardware for Finite Fields

• Custom Multiplier/Adder Designs:

  • Normal Basis Multiplication: Efficient for GF(2^m) using cyclic shifts.

  • Polynomial Basis: Use combinational logic for reduction (e.g., ** Mastrovito multiplier** for area efficiency).

• Trade-offs:

  • Area vs Speed: Parallel multipliers (large area, low latency) vs serial (small area, high latency).

  • Security: Constant-time designs to prevent timing SCA.

Polynomial Identity Testing in Hardware Security

• Formal Verification: Prove that implemented circuit computes polynomial P identical to specification.

• Probabilistic Checking: Use Schwartz-Zippel on circuit inputs to detect malicious modifications (hardware trojans).

• Applications:

  • Trojan Detection: Compare golden polynomial P_gold with implemented P_impl. If P_gold - P_impl ≠ 0, trojan likely.

  • IP Authentication: Verify that third-party IP computes correct polynomial.

[!TIP]

Integration: Link polynomial testing to hardware trojan detection—a key application. For finite field multipliers, mention Mastrovito or Karatsuba for large m.

Final Exam Strategy:

• PUF & SCA are highest weight—master types, attacks, countermeasures.

• DES DPA is a must-know case study.

• GF(4) construction is a frequent 7-mark question—practice steps.

• Fault tolerance diagram: Sketch TMR with voter and error detection.

• Always connect design techniques to attacks (e.g., ECC in PUFs counters reliability issues).