UNIT 3: Computer Organization & Architecture

I. FUNDAMENTAL COMPUTER STRUCTURE & CPU ORGANIZATION

Basic Functional Units of a Computer

A computer consists of five core functional units that work together:

1. Input Unit: Accepts data/instructions from external world (e.g., keyboard, mouse). Converts to machine-readable form.

2. Memory Unit (Main/Primary): Stores programs and data. Classified as RAM (volatile, read/write) and ROM (non-volatile, read-only).

3. Arithmetic and Logic Unit (ALU): Performs all arithmetic (+, -, ×, ÷) and logical (AND, OR, NOT, comparisons) operations.

4. Control Unit (CU): Directs and coordinates all operations. Fetches, decodes, and executes instructions. Generates control signals.

5. Output Unit: Converts machine-coded results to human-readable form (e.g., monitor, printer).

[!TIP] Exam Focus: Be prepared to draw the block diagram showing interaction of these five units.

General Register Organization

Registers are small, fast storage locations inside the CPU for temporary data/instruction holding.

• Special-Purpose Registers:

  • MAR (Memory Address Register): Holds the address of memory location to be accessed.

  • MDR (Memory Data Register): Holds data to be written to or read from memory.

  • IR (Instruction Register): Holds the current instruction being executed.

  • PC (Program Counter): Holds the address of the next instruction to be fetched.

• General-Purpose Registers (GPRs): Used for holding operands and intermediate results during execution (e.g., AX, BX in x86). Their number and size (16/32/64-bit) define the CPU's register architecture.

[!TIP] Common Pitfall: Do not confuse MAR/MDR with cache. They interface with main memory, not cache.

Basic Structure of a Computer System

• CPU: The brain. Contains CU and ALU.

• Memory System: Hierarchy (Registers → Cache → Main Memory → Secondary Storage).

• I/O Subsystem: Manages communication with external devices via I/O controllers and interfaces.

System Bus Structure

A bus is a group of parallel lines carrying data, address, and control signals.

• Data Bus: Bidirectional. Carries data and instructions between CPU, memory, and I/O. Width (number of lines) determines data transfer volume per cycle.

• Address Bus: Unidirectional (CPU → Memory/I/O). Carries memory/I/O addresses. Width determines maximum addressable memory space ($$\displaystyle 2^{\text{width}} $$ locations).

• Control Bus: Carries control signals (Read, Write, Interrupt, Clock, etc.) to coordinate operations.

[!TIP] Key Formula: Maximum Memory = $$\displaystyle 2^{\text{Address Bus Width}} $$ bytes (if each address points to 1 byte).

Instruction Cycle (Fetch-Decode-Execute)

The process of executing a single instruction.

1. Fetch: PC → MAR → Memory → MDR → IR. PC incremented.

2. Decode: CU decodes opcode in IR, determines operation and operands.

3. Execute: CU sends control signals to ALU/memory/I/O to perform the operation.

4. Interrupt: If an interrupt occurs, current PC/PSW saved, ISR executed, then return.

Flowchart:

Start → Fetch → Decode → Execute → Interrupt? → Yes → Service Interrupt → Return → Next Instruction

                                     ↓ No

                              Next Instruction

[!TIP] Exam Question: Always include the Interrupt check as a separate step in the cycle flowchart.

II. INSTRUCTION SET ARCHITECTURE (ISA) & FORMATS

Instruction Set Architecture (ISA)

• Definition: The interface between hardware and software. It defines all programmer-visible components (registers, memory, data types) and the set of instructions the processor can execute.

• Role: Acts as a contract. Software (compiler, OS) is written for an ISA; different CPUs can implement the same ISA (e.g., x86: Intel, AMD).

Instruction Formats

The binary layout of an instruction. Common types based on number of address fields:

Design Considerations: Instruction length, number of addresses, addressing modes, and opcode size trade-off between code density and hardware complexity.

Addressing Modes

Specifies how the operand for an instruction is located.

[!TIP] Exam Focus: For each mode, be ready to give an example and state how many memory accesses are needed to get the operand.

III. CONTROL UNIT DESIGN

Hardwired Control Unit

• Principle: Control signals are generated by fixed logic circuits (gates, decoders). The instruction decoder and a sequence counter generate timing signals based on a state diagram.

• Block Diagram:

  DiagramCANVAS: A diagram showing Instruction Register feeding into a Decoder. The Decoder outputs, along with timing signals from a Sequence Counter/Clock, go into a "Hardwired Logic" block (combinational logic). This block outputs the set of Control Signals (e.g., Read, Write, ALUop, etc.).

• Advantages: Fast (no memory access for microcode). Efficient for simple/complex ISAs with good optimization.

• Disadvantages: Inflexible (difficult to modify/debug). Design complexity increases exponentially with instruction set. Not suitable for complex ISAs.

Micro-programmed Control Unit

• Principle: Control signals are stored as microinstructions in a Control Memory (CM). A micro-program (sequence of microinstructions) generates control signals for each machine instruction.

• Key Terms:

  • Control Memory (CM): Stores microprogram. Usually ROM.

  • Micro-instruction: A word in CM. Contains bits for control signals (vertical) or micro-commands (horizontal).

  • Micro-program: A sequence of microinstructions that implements one machine instruction.

  • Micro-program Sequencer: Generates address of next microinstruction (next-address logic).

• Advantages: Flexible, easy to design/debug/modify. Simplifies handling of complex instructions.

• Disadvantages: Slower (extra memory access per microinstruction). Requires CM storage.

Comparison: Hardwired vs. Micro-programmed

[!TIP] Exam Question: This comparison is very high frequency. Draw a table in your answer.

Microprogram Sequencer

Generates the address for the next microinstruction.

• Functions: Incrementing, Conditional Branching, Subroutine Call/Return.

• Types:

  1. Incrementing: Simple counter (PC-like).

  2. Conditional: Uses condition bits (from ALU flags) for branch decisions.

  3. Subroutine: Supports micro-subroutines (push/pop micro-PC).

Control Word

• Definition: The binary word that represents all control signals active at a given time.

• Hardwired: The output of the combinational logic block at a cycle.

• Microprogrammed: One field/format of a microinstruction. Can be vertical (encoded, few bits) or horizontal (one bit per signal, wide, fast).

IV. ARITHMETIC & LOGIC UNIT (ALU) OPERATIONS

Floating-Point Arithmetic (Addition/Subtraction)

Representation: $$\displaystyle N = (-1)^s \times M \times 2^E $$ (Sign bit s, Mantissa M, Exponent E). Algorithm for Addition/Subtraction (for $A \pm B$):

1. Align Exponents: Shift the mantissa of the number with smaller exponent right until exponents are equal. (Loss of precision possible).

2. Add/Subtract Mantissas: Perform operation on aligned mantissas.

3. Normalize Result: Shift result mantissa left/right to have one non-zero digit before the binary point. Adjust exponent accordingly.

4. Round: Apply rounding (e.g., guard, round, sticky bits) to fit mantissa in available bits.

5. Check for Underflow/Overflow: Adjust exponent if it goes out of range.

[!TIP] Diagram: Be ready to draw the flowchart for these 5 steps.

Stack Operations in CPU

• Implementation: Stack is a LIFO structure in memory. CPU uses a Stack Pointer (SP) register holding the address of the top.

• PUSH: SP ← SP - size (for downward stack), M[SP] ← Operand.

• POP: Operand ← M[SP], SP ← SP + size.

• Example (x86): PUSH AX decrements SP by 2, stores AX at [SS:SP]. POP BX loads BX from [SS:SP], increments SP by 2.

• Uses: Function call/return (saving return address, parameters), local variables, interrupt handling.

Decimal/BCD Arithmetic

• BCD (Binary-Coded Decimal): Each decimal digit (0-9) is represented by 4 binary bits.

• Addition: Add BCD numbers as binary. If result > 9 or carry-out from 4th bit, add 0110 (6) to correct and generate carry.

• Subtraction: Use 10's complement or 9's complement methods.

V. MEMORY HIERARCHY & CACHE MEMORY

Memory Hierarchy Concept

A pyramid of storage levels based on speed, cost, and volatility.

Registers (Fastest, Smallest, Costliest) 

    ↓

Cache (SRAM) 

    ↓

Main Memory (DRAM) 

    ↓

Secondary Storage (HDD/SSD) (Slowest, Largest, Cheapest)

• Need: Bridge the speed gap between fast CPU and slow main memory. Exploit Principle of Locality (Temporal: reuse recent data; Spatial: use nearby data).

Cache Memory

• Importance: Reduces average memory access time. Holds frequently used blocks of main memory.

• Principle of Locality: Programs tend to access a small set of data/instructions repeatedly over a short time.

Cache Mapping Techniques

Determines where a block from main memory can be placed in cache.

[!TIP] Formula: In N-way set-associative, #Sets = Cache Size / (Block Size × N).

Cache Levels (L1, L2, L3)

Associative Memory

• Concept: Memory where content (not address) determines location. Search is done in parallel.

• Organization: Each cell has a key (address) and value (data). A comparator matches input key with all stored keys simultaneously.

• Hardware: Uses match lines and search lines. More expensive than RAM.

• Comparison with Cache: Cache uses associative lookup within a set/line, but is still indexed by address bits. True associative memory is content-addressable from any input.

Effective Access Time (EAT) Calculation

$$ \boxed{\text{EAT} = (\text{Hit Ratio} \times \text{Cache Access Time}) + (\text{Miss Ratio} \times \text{Miss Penalty})} $$

Where:

• Miss Penalty = Time to access main memory + transfer block + possibly update cache.

• Hit Ratio (h) = Fraction of accesses found in cache.

• Miss Ratio = 1 - h.

Example: If $$\displaystyle h = 0.95 $$, $$\displaystyle t_c = 10\,ns $$, $$\displaystyle t_m = 100\,ns $$, then:

$$ \text{EAT} = (0.95 \times 10) + (0.05 \times 100) = 9.5 + 5 = \boxed{14.5\,ns} $$

Internal Organization of RAM & ROM Chips

• Address Lines: Select a specific row/column/cell.

• Data Lines: Bi-directional for read/write.

• Control Pins:

  • Chip Select (CS): Enables the chip.

  • Read (RD) / Write (WR): Determines operation direction.

  • Output Enable (OE): Tri-states output drivers (for shared bus).

VI. INPUT/OUTPUT (I/O) ORGANIZATION

Interrupts

• Definition: An asynchronous event that causes the CPU to temporarily suspend its current program and execute a special routine (Interrupt Service Routine - ISR).

• Need: Allows CPU to respond to urgent I/O events (e.g., keypress, data ready) without constant polling (wasting CPU cycles).

• Types:

  • Maskable vs. Non-maskable (NMI): Can CPU ignore it? NMI (e.g., hardware failure) cannot be masked.

  • Software vs. Hardware: Software interrupt (INT n instruction) vs. Hardware signal (from device).

  • Vectored vs. Non-Vectored: Does interrupt provide its ISR address? Vectored does (e.g., 8086's INTR).

Interrupt Handling (Process & Priority)

1. Interrupt Occurs: Device sends signal to CPU.

2. Finish Current Instruction: CPU completes current instruction.

3. Save Context: PC and PSW (Program Status Word) pushed onto stack.

4. Branch to ISR: Load PC with ISR address (from Interrupt Vector Table for vectored interrupts).

5. Execute ISR: Service the device.

6. Return: IRET instruction pops saved PC/PSW, resumes original program.

Priority Handling: Multiple simultaneous interrupts resolved by:

• Software Polling: CPU asks each device in priority order.

• Daisy Chain (Hardware): Devices in series, INTA signal cascades.

• Parallel Priority (Interrupt Controller): e.g., 8259 PIC, uses priority encoder.

8086 Specifics:

• INTR: Maskable, general-purpose interrupt. Type determined by external interrupt controller (like 8259).

• NMI: Non-maskable. Type 2 interrupt.

• Interrupt Vector Table (IVT): Located at 0000:0000 in memory. Contains 4-byte pointers (CS:IP) for each of 256 interrupt types.

Direct Memory Access (DMA)

• Working: A DMA Controller takes over the system bus to transfer data directly between I/O device and memory, bypassing the CPU.

• DMA Controller: Has registers: DR (Data Register), MAR, WC (Word Count), Control/Status.

• Requirements: CPU must be disabled (or cycles "stolen") during transfer. DMA controller must be initialized by CPU (set source, destination, count).

• Transfer Modes:

  • Burst/Block: Entire block transferred in one DMA cycle. Fast, CPU idle long.

  • Cycle Stealing: DMA takes one bus cycle at a time, interleaving with CPU. Slower, but CPU not blocked.

  • Transparent: DMA only when CPU not using bus.

[!TIP] Key Difference from Programmed I/O: In PIO, CPU executes IN/OUT for every byte/word. In DMA, CPU sets up DMA, then DMA handles bulk transfer.

Data Transfer Methods

Serial vs. Parallel Transfer

Strobe Method (Handshaking)

A simple asynchronous synchronization method for data transfer.

• Sender: Places data on line, sends a strobe pulse.

• Receiver: Reads data when it detects the strobe pulse.

• Limitation: No acknowledgment from receiver (unlike full handshaking with Request/Acknowledge).

I/O Channels

A specialized processor (channel) that manages I/O operations independently.

• Concept: Offloads I/O tasks from CPU. CPU sends channel program (list of I/O commands).

• Types:

  • Selector Channel: Connects one high-speed device (e.g., tape drive) at a time to main memory. Dedicated path.

  • Multiplexor Channel: Connects multiple slower devices (e.g., terminals) to main memory, interleaving their operations. Time-shared path.

VII. ADVANCED CPU ARCHITECTURES & PARALLELISM

RISC vs. CISC Architectures

Instruction-Level Parallelism (ILP) vs. Thread-Level Parallelism (TLP)

Pipelining

• Concept: Break instruction execution into stages (e.g., Fetch, Decode, Execute, Memory, Writeback). Multiple instructions overlap in different stages.

• Speedup (Ideal): If k stages, speedup ≈ k (ignoring hazards).

• Hazards:

  • Structural: Resource conflict (two instructions need same unit).

  • Data: Dependency (e.g., ADD R1, R2 followed by SUB R3, R1).

  • Control: Branch/jump changes PC, instructions after branch are wrong.

• Space-Time Diagram (4-stage):

  
  Cycle: 1   2   3   4   5   6   7
  
  I1:    F   D   E   W
  
  I2:        F   D   E   W
  
  I3:            F   D   E   W
  
  I4:                F   D   E   W
  
  

  Throughput = 1 instruction/cycle after pipeline fill.

Multicore Processor Architecture

• Basic Structure: Multiple independent CPU cores (each with own ALU, CU, L1 cache) integrated on a single chip. Share L2/L3 cache and memory controller.

• Advantages:

  • Increased throughput (true parallelism for multi-threaded apps).

  • Better utilization of silicon area.

  • Lower power per core vs. single huge core.

  • Fault tolerance (one core failure may not crash system).

Vector Processing & ARM Architecture

• Vector Processing: Single instruction operates on entire vectors/arrays (SIMD - Single Instruction, Multiple Data). E.g., add two arrays of 64 floats with one VADD instruction. Faster than scalar pipelining for data-parallel tasks (multimedia, scientific).

• ARM Processor Architecture (Key Features):

  • Load-Store Architecture: Only load/store instructions access memory. ALU ops only on registers.

  • Register Set: 16-32 32-bit general-purpose registers (R0-R15). R13=SP, R14=LR, R15=PC.

  • Fixed 32-bit Instruction Length (in ARM mode).

  • Conditional Execution: Most instructions can be conditionally executed (reduces branches).

  • Power Efficient: Dominant in mobile/embedded (phones, IoT).

VIII. SECONDARY STORAGE & SPECIALIZED MEMORIES

Optical Disks

• Principle: Data stored as pits and lands on a spiral track. Read by laser beam reflecting differently from pits/lands.

• CD (Compact Disc): ~700 MB, 120mm diameter. Single layer, single-sided.

• DVD (Digital Versatile Disc): Uses smaller pits & dual-layer. 4.7 GB (single-layer), 8.5 GB (dual-layer).

• Blu-ray: Uses blue-violet laser (shorter wavelength), allows smaller pits. 25 GB (single-layer), 50 GB (dual-layer). Used for HD video.

[!TIP] Low Frequency: This topic appears as a short 3-mark question. Know the trend: Capacity increases with shorter wavelength and multi-layer technology.

END OF UNIT 3 NOTES