Computer Organization & Architecture (CY-504 (C)) - Unit 1 Short Notes

UNIT 1: Computer Organization & Architecture

1. Basic Computer Structure & Functional Units

A digital computer system consists of five basic functional units: Input Unit, Memory Unit, Arithmetic and Logic Unit (ALU), Control Unit (CU), and Output Unit. These units are interconnected via a system bus.

Block Diagram of a Computer System

Core Components:

• CPU: Contains CU and ALU. Fetches, decodes, executes instructions.

• Memory Unit: Stores programs and data (main memory).

• I/O Subsystem: Interfaces with external devices (keyboard, monitor, disk).

• System Bus: Communication pathway for data, addresses, and control signals.

DiagramCANVAS: Von Neumann architecture block diagram showing CPU (with CU and ALU), Memory, I/O devices, all connected via a central System Bus (split into Address Bus, Data Bus, Control Bus). Arrows show data flow between units.

System Bus Structure

The system bus is logically divided into three independent buses:

Key Point: The width of the address bus determines the maximum memory capacity. For example, a 32-bit address bus can address $$\displaystyle 2^{32} $$ locations = 4 GB (if each location is 1 byte).

2. Central Processing Unit (CPU) Organization

General Register Organization

Registers are fast, small storage locations inside the CPU. Key registers include:

Register File: A set of general-purpose registers organized as a small, fast memory. Access is typically via register-select lines.

Stack Operations

A stack is a LIFO (Last-In-First-Out) memory structure, often implemented in CPU registers or main memory.

• Push: Decrement stack pointer (SP), then store data at new top.

• Pop: Read data from top, then increment SP.

• Stack-Based Execution: Instructions like ADD pop two operands, push result. Used in zero-address instruction formats.

Example (0-address):

PUSH A → PUSH B → ADD → POP C

Stack after PUSH A: [A]

After PUSH B: [B, A]

After ADD: [A+B]

After POP C: C = A+B

Instruction Cycle

The CPU repeatedly performs an instruction cycle (also called fetch-decode-execute cycle).

1. Fetch: Get instruction from memory address in PC → IR. PC ← PC + 1.

2. Decode: Interpret opcode in IR, determine operation and operands.

3. Execute: Perform operation (ALU, memory access, I/O, etc.).

4. Interrupt Handling: If an interrupt occurs, save state, service interrupt, restore state.

Flowchart:

Start → Fetch → Decode → Execute → Interrupt? → Yes → Service → Return → No → Next Instruction → End.

Control Unit (CU)

Generates control signals to coordinate all CPU operations.

Hardwired Control

• Design: Fixed logic circuits (gates, flip-flops) generate control signals directly from instruction decoder and timing unit.

• Block Diagram: Instruction register → Decoder → Timing Unit → Control Signal Generator.

• Advantages: Fast (no memory access for microinstructions), efficient.

• Disadvantages: Inflexible (difficult to modify instruction set), complex design for large ISAs.

Microprogrammed Control

• Design: Control signals are stored as microinstructions in a control memory (CM).

• Microinstruction: Contains control bits for one micro-operation (e.g., PC → AR, ALU ADD).

• Microprogram Sequencer: Determines next microinstruction address (sequential, branch based on flags).

• Control Word (CW): The binary microinstruction. Format can be horizontal (many bits, parallel ops) or vertical (encoded, fewer bits).

• Advantages: Flexible (easy to modify ISA), simpler design.

• Disadvantages: Slower (extra memory access per microinstruction), overhead.

Comparison Table:

| Feature | Hardwired Control | Microprogrammed Control |

|-----------------------|--------------------------|---------------------------|

| Speed | Fast | Slower (due to CM access) |

| Flexibility | Low (fixed logic) | High (modify microcode) |

| Design Complexity | High for complex ISAs | Lower |

| Cost | Lower (no CM) | Higher (CM + sequencer) |

| Debugging/Modification| Difficult | Easier |

Instruction Set Architecture (ISA)

ISA defines the programmer-visible interface: instructions, registers, memory model, addressing modes.

Instruction Formats

Based on number of address fields:

Addressing Modes

Specify how operand address is calculated.

Exam Tip: Distinguish direct (address field = operand address) vs indirect (address field = pointer to operand address).

3. Arithmetic Operations

Fixed-Point Arithmetic

Numbers with implicit decimal/binary point at a fixed position.

• Unsigned Addition/Subtraction: Straightforward binary addition/subtraction; watch for carry/borrow.

• Signed Numbers (2's complement): Addition same as unsigned; subtraction via 2's complement of subtrahend.

• Multiplication/Division: Shift-and-add (multiplication), shift-and-subtract (division). More complex than floating-point for large ranges.

Floating-Point Arithmetic

Represents numbers as: $$\displaystyle \pm S \times M \times 2^E $$ (sign, mantissa, exponent). Follows IEEE 754 standard.

IEEE 754 Single Precision (32-bit)

• Sign (S): 1 bit (0 = positive, 1 = negative).

• Exponent (E): 8 bits, biased by 127. Actual exponent = E - 127.

• Mantissa (M): 23 bits, normalized with implicit leading 1 (so 24-bit precision).

Normalized Value: $$\displaystyle (-1)^S \times (1.M)_2 \times 2^{(E-127)} $$

Example: 0x40490FDB ≈ 3.14159 (S=0, E=130→3, M=0.10010010000111111011011₂).

Floating-Point Addition/Subtraction Flowchart

1. Align exponents: Shift mantissa of smaller exponent right until exponents equal.

2. Add/Subtract mantissas: Depending on sign bits.

3. Normalize result: Shift mantissa left/right to restore leading 1; adjust exponent.

4. Round: To nearest (default), using guard, round, sticky bits.

5. Check overflow/underflow: Exponent too large/small.

Rounding Modes: Round to nearest even (default), toward zero, toward ±∞.

Decimal Arithmetic

• BCD (Binary-Coded Decimal): Each decimal digit (0-9) encoded in 4 bits.

• Operations: ALU must support BCD addition (adjust after binary add: if sum >9 or carry, add 6). Example: 9+1 in BCD = 1001 + 0001 = 1010 (invalid) → add 0110 → 1 0000 (carry, result 0).

• Use: Financial calculations where exact decimal representation is critical.

4. Memory System

Main Memory Organization

• RAM (Random Access Memory):

  • SRAM (Static RAM): Uses flip-flops, fast, expensive, volatile. Used for cache.

  • DRAM (Dynamic RAM): Uses capacitors, slower, cheaper, needs refresh. Used for main memory.

• ROM (Read-Only Memory):

  • PROM: Programmable once.

  • EPROM: Erasable with UV light.

  • EEPROM: Electrically erasable.

  • Flash: Block-wise erasable, non-volatile (USB, SSD).

Internal Organization: Memory chips are organized as 2D arrays of cells. A memory address selects a row (via row address strobe, RAS) and column (column address strobe, CAS). Word size = number of bits per row.

Memory Hierarchy

Based on locality of reference (temporal & spatial):

• Levels: Registers (fastest, smallest) → L1/L2/L3 Cache → Main Memory (DRAM) → Secondary Storage (SSD/HDD).

• Goal: Achieve near-register speed at near-disk cost.

Cache Memory

Small, fast memory between CPU and main memory. Stores frequently accessed blocks.

Mapping Techniques

Example: 4-way set-associative: block address mod (number of sets) selects set; then search 4 lines in parallel.

Cache Levels

• L1 Cache: Split into L1i (instruction) and L1d (data). Fastest, smallest (32-64 KB), on-core.

• L2 Cache: Larger (256-512 KB), may be on-core or shared.

• L3 Cache: Largest (several MB), shared among cores. Slower than L2 but faster than RAM.

Associative Memory

• Organization: Memory accessed by content (data), not address. Each location has a tag (key) and data.

• Operation: Search all locations in parallel for a given key; if match, return associated data.

• Difference from Cache: Cache is a speed buffer using associative lookup to reduce miss penalty; associative memory is a primary storage for fast search (e.g., TLB, database).

Performance Evaluation

• Hit Ratio (h): Fraction of memory accesses found in cache.

• Miss Ratio (m): 1 - h.

• Effective Access Time (EAT):

$$ \text{EAT} = h \times t_c + (1-h) \times t_m $$

where $$\displaystyle t_c $$ = cache access time, $$\displaystyle t_m $$ = main memory access time (including block transfer time on miss).

Numerical Example:

Given: h = 95% = 0.95, $$\displaystyle t_c $$ = 10 ns, $$\displaystyle t_m $$ = 100 ns.

EAT = 0.95×10 + 0.05×100 = 9.5 + 5 = 14.5 ns.

\boxed{\text{EAT} = h \cdot t_c + (1-h) \cdot t_m}

5. Input/Output (I/O) Organization

I/O Methods

Interrupt Handling

• Interrupt Priority: Hardware/software priority scheme (e.g., daisy-chain, parallel poll). Higher priority interrupts can preempt lower.

• Interrupt Service Routine (ISR): Code executed on interrupt. Saves CPU registers, services device, restores state, returns via IRET.

DMA Working Principle

1. CPU programs DMA controller: source/destination address, transfer count, control (read/write).

2. DMA requests bus control (via HOLD signal).

3. CPU releases bus (via HLDA), DMA performs transfers (cycle stealing or burst mode).

4. DMA releases bus, interrupts CPU on completion.

Data Transfer Techniques

I/O Channels

A channel is a dedicated processor (I/O channel) that executes channel programs (I/O instructions) independently. CPU offloads I/O tasks to channel, which manages multiple devices. More powerful than DMA (can perform simple processing).

6. Advanced Processor Concepts

CISC vs. RISC

Instruction-Level Parallelism (ILP) vs. Thread-Level Parallelism (TLP)

Pipelining

• Basic Concept: Divide instruction processing into stages (Fetch, Decode, Execute, Memory, Write-back). Multiple instructions in different stages overlap.

• Space-Time Diagram (4-segment pipeline):

  
  Time → | Stage1 | Stage2 | Stage3 | Stage4 |
  
  Inst1 |   F    |   D    |   E    |   W    |
  
  Inst2 |        |   F    |   D    |   E    |
  
  Inst3 |        |        |   F    |   D    |
  
  Inst4 |        |        |        |   F    |
  
  

• Pipeline Hazards:

  • Structural: Resource conflict (e.g., two instructions need memory at same time).

  • Data: Dependency (e.g., ADD R1, R2 followed by SUB R3, R1). Solved by forwarding/stalling.

  • Control: Branch instructions change PC; pipeline fetches wrong instructions. Solved by branch prediction, delayed slots.

Vector Processing

• Concept: Process single instruction on multiple data elements (SIMD - Single Instruction, Multiple Data). Uses vector registers (arrays of data) and vector functional units.

• Applications: Scientific computing, graphics, ML (matrix operations).

• Example: VADD V1, V2, V3 adds corresponding elements of two vectors (V2, V3) and stores in V1.

7. Specific Processor Architectures

8086 Microprocessor

• Interrupt Structure:

  • Software Interrupts: INT n (type 0-255), INTO (overflow), single-step (Trap Flag).

  • Hardware Interrupts:

    • INTR: Maskable general interrupt.

    • NMI: Non-maskable interrupt (higher priority, e.g., power failure).

• Interrupt Handling Mechanism:

  1. Interrupt signal received.

  2. CPU completes current instruction.

  3. Flags, CS, IP pushed onto stack.

  4. IF (Interrupt Flag) cleared (mask further INTR).

  5. Interrupt type obtained (from bus or INT instruction).

  6. CS:IP ← contents of Interrupt Vector Table (IVT) at 0000:0000 (4 bytes per vector: IP, CS).

  7. ISR executed.

  8. IRET pops CS, IP, flags, returns.

ARM Processor

• Basic Architecture: RISC, load-store architecture (only load/store access memory).

• Key Features:

  • Register Set: 16 general-purpose registers (R0-R15). R13=SP, R14=LR, R15=PC.

  • Fixed 32-bit instruction length (ARM state) or 16-bit (Thumb).

  • Conditional Execution: Most instructions can be conditionally executed (suffix like EQ, NE).

  • Pipelined: Typically 3-5 stage pipeline.

  • Low Power: Designed for embedded systems.

8. Additional Topics from Past Papers

Microprogram Sequencer

• Role: Generates the address of the next microinstruction in control memory.

• Inputs: Current microinstruction address, condition codes (from ALU flags), branch control fields.

• Operation: Usually increments address sequentially; on branch, loads new address from microinstruction or from a separate register (e.g., subroutine return address stack).

• Types: Incrementer-only, with branch logic, with microprogram stack (for subroutines).

Optical Disks

• Principle: Use laser light to read/write pits/lands on reflective surface.

• Types:

  • CD: 700 MB, 780 nm laser, pits ~0.5 µm.

  • DVD: 4.7 GB (single layer), 650 nm laser, smaller pits.

  • Blu-ray: 25 GB (single layer), 405 nm blue-violet laser, even smaller pits.

• Access: Rotational, with constant linear velocity (CLV) or constant angular velocity (CAV).

Vector Processing (Detailed)

• Vector Processor: Has vector registers (e.g., 64 elements of 64 bits each) and pipelined vector functional units (add, multiply).

• Operation: Single vector instruction operates on entire arrays. Reduces instruction fetch/decode overhead.

• Example: Cray-1, modern SIMD extensions (SSE, AVX in x86; NEON in ARM).

Control Word

• Definition: The binary representation of a microinstruction. Each bit (or field) controls a specific CPU resource (e.g., ALU_OP=ADD, READ_MEM, REG_WRITE).

• Format:

  • Horizontal: One bit per control signal. Long (e.g., 100+ bits), allows maximum parallelism.

  • Vertical: Encoded fields (e.g., 4 bits for ALU operation). Shorter, but requires decoding, less parallel.

Exam Tips & Common Pitfalls:

• Addressing Modes: Confusing direct (address field = operand address) with indirect (address field = pointer to operand address). Practice examples.

• Cache Mapping: Remember formulas: Direct mapping → cache line = block address mod (number of lines). Set-associative → set = block address mod (number of sets).

• Floating-Point: Normalization requires leading 1 in mantissa; exponent bias (127 for single, 1023 for double).

• EAT Calculation: Miss penalty includes main memory access time, not just cache miss time. If block transfer needed, $$\displaystyle t_m $$ includes transfer time.

• Pipeline Hazards: Data hazards solved by forwarding/bypassing; control hazards by branch prediction.

• Hardwired vs Microprogrammed: Hardwired is faster but inflexible; microprogrammed is slower but easily modified (e.g., for new instructions).

• DMA vs Interrupts: In DMA, CPU only initializes and gets final interrupt; data transfer occurs without CPU. In interrupt-driven I/O, CPU handles every byte/word.