Computer Organization & Architecture (CY-504 (C)) - Important Questions

Core concept of memory system; repeatedly asked in past papers focusing on cache role in performance.

Direct question on associative memory distinguishing it from cache — tests understanding of content-addressable memory concepts.

Numerical/analytical question on effective access time using hit ratio and access latencies; tests basic cache performance calculation.

Detailed conceptual question on cache mapping methods (direct, associative, set-associative) including merits and demerits.

Question targeting levels of on-chip/off-chip caches and their design trade-offs (L1, L2, L3).

Hardware organization question requiring diagrams and explanations of RAM and ROM internal structures.

Short/definition style question appearing in past paper; preserves original phrasing.

Broad, high-frequency aggregated topic covering instruction-level and thread-level parallelism, pipelining, and ISAs (RISC/CISC/ARM). High priority for exam preparation.

Comparative question asking for differences and diagrams — common conceptual topic on control unit design.

Registers are fundamental to CPU datapath and control; repeated topic testing knowledge of register roles and organization.

Interrupts and handling mechanisms (including a microprocessor case study) is a standard exam topic on control flow and exception handling.

Instruction Set Architecture basics and addressing modes are core ISA topics frequently examined.