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CY-504 (C) · Computer Organization & Architecture/Important Questions

Computer Organization & Architecture (CY-504 (C)) - Important Questions

  1. Unit 47 Marks Medium Priority Asked: 2024, 2023

    Define Interrupts and explain their types. How are interrupts handled in a microprocessor, specifically in the case of the 8086 microprocessor?

    Direct question from DEC 2024 paper: defines interrupts and asks handling in 8086 microprocessor.

  2. Unit 47 Marks Medium Priority Asked: 2024, 2023

    Differentiate between a hardwired control unit and a micro-programmed control unit with suitable diagrams.

    Directly repeated question asking comparison between two control-unit implementation styles; appeared in multiple papers.

  3. Unit 47 Marks Medium Priority Asked: 2024, 2023

    Explain the concept of Memory Hierarchy in computer architecture. Why is cache memory considered crucial in improving system performance?

    Core topic on performance; seen repeatedly in past papers and emphasized in heatmap analytics.

  4. Unit 47 Marks Medium Priority Asked: 2024, 2023

    Describe the general register organization in CPU architecture. Explain the role of registers like Memory Register, Instruction Register, and Program Counter.

    Standard register-organization question appearing multiple times in past papers and analytics.

  5. Unit 47 Marks Low Priority Asked: 2023

    Illustrate the flow chart of Instruction cycle and explain.

    Short direct question from NOV 2023 requiring a flow-chart and explanation of instruction cycle.

  6. Unit 47 Marks Low Priority Asked: 2023

    Control word

    Short direct one-line topic seen in NOV 2023 paper (expects definition and role of control word).

  7. Unit 47 Marks Low Priority Asked: 2023

    Micro program sequencer

    Short direct one-line topic from NOV 2023 asking about the microprogram sequencer component.

  8. Unit 47 Marks High Priority Asked: 2024, 2023

    Explain I/O organization: DMA, programmed I/O, interrupt-driven I/O. Compare serial and parallel data transfer modes and list advantages of each.

    Aggregated high-frequency I/O topic from heatmap and past papers covering DMA, programmed I/O and interrupt-driven I/O plus transfer modes.

  9. Unit 47 Marks Medium Priority Asked: 2024

    What is Instruction Set Architecture (ISA)? Explain the various types of addressing modes with examples.

    Frequently asked ISA question in recent papers; asks definition and addressing modes with examples.

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