Computer Organization & Architecture (CY-504 (C)) - Important Questions
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Unit 37 Marks High Priority Asked: 2023, 2024
Explain the concept of Memory Hierarchy in computer architecture. Why is cache memory considered crucial in improving system performance?
Core topic; highly frequent in past papers (heatmap frequency 7).
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Unit 37 Marks High Priority Asked: 2023, 2024
Explain cache mapping techniques and cache replacement policies with examples.
Directly targets frequent subtopics: cache mapping and replacement; appears repeatedly in Unit 3 questions.
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Unit 37 Marks Medium Priority Asked: 2024
Explain associative memory and secondary memory technologies.
Topic shown in analytics as a repeated theme in 2024 papers (associative memory and secondary storage).
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Unit 37 Marks Medium Priority Asked: 2024
What is Instruction Set Architecture (ISA)? Explain the various types of addressing modes with examples.
Repeated in DEC 2024 papers; standard ISA and addressing modes question.
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Unit 37 Marks Medium Priority Asked: 2024
Explain the difference between RISC and CISC architectures. Why are RISC processors generally preferred in modern computing?
Asked in DEC 2024; core comparison question between instruction set philosophies.
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Unit 37 Marks Medium Priority Asked: 2024
Explain the concept of Instruction-Level Parallelism (ILP) and how it differs from Thread-Level Parallelism (TLP). Provide examples to illustrate the difference.
Covers parallelism concepts; appeared in DEC 2024 paper as a long-answer question.
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Unit 33 Marks Medium Priority Asked: 2024
Micro program sequencer
Short answer item from DEC 2024; core microprogramming component.
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Unit 33 Marks Medium Priority Asked: 2024
Instruction Formats
Short answer item from DEC 2024; fundamental instruction representation topic.
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Unit 37 Marks Medium Priority Asked: 2023
What is Interrupt? Explain how interrupts are serviced using priorities?
Asked in NOV 2023; focuses on interrupt handling and priority-based servicing.
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Unit 37 Marks High Priority Asked: 2023, 2024
Describe the general register organization in CPU architecture. Explain the role of registers like Memory Register, Instruction Register, and Program Counter.
Appeared multiple times; core CPU register topics frequently tested in Unit 3.
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Unit 37 Marks Medium Priority Asked: 2023, 2024
Differentiate between a hardwired control unit and a micro-programmed control unit with suitable diagrams.
Repeated in past papers; classic control-unit design question requiring diagrams.
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